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| F71808E F71808E Super Hardware Monitor + LPC I/O with Power Saving Control Release Date: Aug, 2010 Version: V0.21P Aug, 2010 V0.21P F71808E F71808E Datasheet Revision History Version V0.10P V0.11P V0.12P V0.13P V0.14P V0.15P Date 2009/6 2009/7 2009/7 2009/8 2009/8 2009/8 Page 76 12 28 12 31 34 36 37 41 49 52 76 34 10 79 86 88-89 7,84 86 41,77 90 V0.20P 2010/01 88,90,92 35 79-81 5, 18, 40 41 10 6-9, 12-13, 30 20, 23 42 43 44 47 48 49 58 61 64 Revision History Preliminary Version Update Package Dimensions Add EuP relative registers Rvise typo Revise 3VSBSW# description Add 3VBSW# timing chart Add Pin 27 internal pull-high description Modify register typo. Revise CR27 default to 1 Add "Power Saving" in LDN=0A description Revise CR2Ah bit[3:2] description Revise CR2Bh bit3 and 1 description V0.16P 2009/9 Remove redundant register CR02h[2] Revise CR94h description V0.17P V0.18P 2009/10 2009/11 V0.19P 2009/12 V0.21P 2010/08 Add bit 6 description in CR9Bh Swap LDN(CR=0Ah) CRF1h and CRF2h Add Chip/Vendor ID register description Remove pin 57 WDT_EN function Add EuP register index E8/EE/EDh Modify TopMarking description for LAB Version Modify application circuit strapping table and UART circuit Modify average operation supply current Modify typo of version identification Reserved Config register index 02h bit 2 and WDT PME register index 07h bit 0. Modify application circuit ( Remove Case Open circuit) Modify application circuit (Remove pin 57), RC protection and typo Modify Configuration Port Select Register (Index 27h, bit0) to TIMING_EN Remove RI# wakeup function Modify typo 1. Update RS485 enable register description 2. Correct Pin Type Remove Ibex and TSI function and pin descriptions Remove Monitor Temp from SMBus Remove TSI Register Description in Device Registers 1. Remove Configuration Register Index 08h 2. Modify Configuration Register Index 0Ah bit 0:1 1. Modify Configuration Register ( Index 0Ch 2. Modify Configuration Register ( Index 0Fh bit 1:0 Modify T1 Over-OVT and Over-High Limit Temperature Select Register ( Index 64h Modify DIODE OPEN Status Register -- Index 6Fh bit 4 Remove index 7Ah - 7Dh Modify FAN1 Temperature Mapping Select - Index AFh [1:0] Modify FAN2 Temperature Mapping Select - Index BFh [1:0] 1. Modify FAN3 Temperature Mapping Select - Index CFh [1:0] Aug, 2010 V0.21P F71808E 2. Remove index E0h - E4h, EDh 67 87 Modify GPIO3 Pin Status Register Index C2h bit 3:2 Update Reference Circuit Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. Aug, 2010 V0.21P F71808E Table of Content 1. General Description .............................................................................................................. 6 2. Feature List ........................................................................................................................... 6 3. Key Specification................................................................................................................... 8 4. Block Diagram....................................................................................................................... 8 5. Pin Configuration .................................................................................................................. 9 6. Pin Description.................................................................................................................... 10 6.1 Power Pin.................................................................................................................. 10 6.2 LPC Interface ............................................................................................................ 10 6.3 UART Function.......................................................................................................... 11 6.4 Hardware Monitor...................................................................................................... 12 6.5 ACPI Function Pins ................................................................................................... 13 6.6 KBC Function ............................................................................................................ 14 6.7 Others ....................................................................................................................... 14 7. Function Description ........................................................................................................... 16 7.1 Power on Strapping Option ....................................................................................... 16 7.2 Keyboard Controller .................................................................................................. 16 7.3 Hardware Monitor...................................................................................................... 18 7.4 ACPI Function ........................................................................................................... 25 7.5 INTEL PECI Function ................................................................................................ 30 7.6 Over Voltage Protection ............................................................................................ 30 7.7 Power Saving Controller ........................................................................................... 30 8. Register Description............................................................................................................ 32 8.1 Global Control Registers ........................................................................................... 35 8.2 UART Registers (CR01)............................................................................................ 40 8.3 Hardware Monitor Register (CR04)........................................................................... 41 8.4 KBC Registers (CR05) .............................................................................................. 65 8.5 GPIO Registers (CR06) ............................................................................................ 66 8.6 WDT Registers (CR07) ............................................................................................. 74 8.7 PME, ACPI, Power Saving Registers (CR0A) ........................................................... 76 9. Electrical Characteristics..................................................................................................... 83 9.1 Absolute Maximum Ratings ...................................................................................... 83 9.2 DC Characteristics .................................................................................................... 83 10.Ordering Information.......................................................................................................... 85 11.Package Dimensions ......................................................................................................... 86 Aug, 2010 V0.21P F71808E 12.Application Circuit .............................................................................................................. 87 Aug, 2010 V0.21P F71808E 1. General Description The F71808E which is the featured IO chip for PC system equippes one UART Port, Hardware Keyboard Controller, Hardware Monitor, ACPI management function and some GPIO pins. The F71808E integrated with hardware monitor, 8 sets of voltage sensor, 3 sets of creative auto-controlling fans and temperature sensor pins for the accurate dual current type temperature measurement for CPU thermal diode or external for temperature sensing. Besides, HWM also integrated Intel PECI interface for new platform temperature reading. For AMD platform, the F71808E provides the power sequence controller function which is selected by register. The F71808E provides flexible features for multi-directional application. For instance, provides GPIO pins which can be programmed by register setting, accurate current mode H/W monitor will be worth in measurement of temperature, provides 3 modes fan speed control mechanism included Auto-Linear, Auto-Stage and Manual Mode for users' selection. A power saving function which is in order to save the current consumption when the system is in the soft off state is also integrated a power saving function. The power saving function supports that system boot-on not only by pressing the power button but also by the wake-up event. When the system enters the S4/S5 state, F71808E can cut off the VSB power rail which supplies power source to the devices like the LAN chip, the chipset, the SIO, the audio codec, DRAM, and etc. The PC system can be simulated to G3-like state when system enters the S4/S5 states. At the G3-like state, the F71808E consumes the 5VSB power rail only. The integrated two control pins are utilized to turn on or off VSB power rail in the G3-like status. The turned on VSB rail is supplied to a wake up device to fulfil a low power consumption system which supports a wake up function. The F71808E is powered by 3.3V and 5VSB voltage, with the LPC interface in 64-TQFP green package. 2. Feature List General Functions Comply with LPC Spec. 1.1 Support DPM (Device Power Management), ACPI Support AMD power sequence controller Provides one UART, Hardware KBC H/W monitor functions Watch Dog Timer function LED blink funciton Intel PECI interface 28 GPIO pins for flexible application 6 Aug, 2010 V0.21P F71808E GPIO22-25 supports High/Low/Pulse/Level mode option GPIO22-25 supports interrupt event by PME/SERIRQ 24/48 MHz clock input Packaged in 64-TQFP and powered by 3.3VCC UART High-speed 16C550 compatible UART with 16-byte FIFOs Fully programmable serial-interface characteristics Baud rate up to 115.2K Keyboard Controller LPC interface support serial interrupt channel 1, 12. Two 16bit Programmable Address fully decoder, default 0x60 and 0x64. Support two PS/2 interface, one for PS/2 mouse and the other for keyboard. Keyboard's scan code support set1, set2. Programmable compatibility with the 8042. Support both interrupt and polling modes. Hardware Gate A20 and Hardware Keyboard Reset. Hardware Monitor Functions 2 dual current type (3) thermal inputs for CPU thermal diode and 2N3906 transistors Temperature range -40~127 Integrate PECI 1.1a spec. 8 sets voltage monitoring (5 external and 3 internal powers) Voltage monitor supports Over Voltage Protection 3 fan speed monitoring inputs 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans) Auto Stage mode ( 2-Limit and 3-Stage)/Auto Linear mode/Manual mode Issue PME# and OVT# hardware signals output WATCHDOG comparison of all monitored values Watch Dog Timer Time resolution minute/second by option Maximum 256 minutes or 256 seconds Output signal from WDTRST# pin Support AMD Power Sequence Controller 7 Aug, 2010 V0.21P F71808E Power Saving Controller ACPI Timing and Power Control Wake-up Supported Package 64-pin TQFP Green Package 3. Key Specification Supply Voltage Average Operating Supply Current 3.0V to 3.6V 8 mA typ. 4. Block Diagram CPU Chipset (NB+SB) Super H/W Monitor + F71808E IDE USB AC'97 Temperature Voltage (OVP) Fan PECI KBC WDT Power Saving I/O LED COM GPIO ACPI AMD Seq. 8 Aug, 2010 V0.21P F71808E 5. Pin Configuration Figure1. F71808E pin configuration 9 Aug, 2010 V0.21P F71808E 6. Pin Description I/O12t I/O12ts5v I/OOD12ts5v I/OD16t5v OD16-u10-5v I/OD12ts5v I/OD12tslv I/O8tslv O8-u47-5v O8 O12 O24 AOUT OD12 OD12-5v OD24 INt5v INts INts5v AIN P - TTL level bi-directional pin with 12 mA source-sink cap ability. - TTL level bi-directional pin with schmitt trigger, 12 mA source-sink capability and 5V tolerance. - TTL level bi-directional pin with schmitt trigger, can select to OD or OUT by register, with 12 mA source-sink capability and and 5V tolerance - TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance. - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.) with schmitt trigger. Output with 12mA sink capability. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.) with schmitt trigger. Output with 8mA drive and 1mA sink capability. - Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. - Output pin with 8 mA source-sink capability. - Output pin with 12 mA source-sink capability. - Output pin with 24 mA source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability. - Open-drain output pin with 12 mA sink capability, 5V tolerance. - Open-drain output pin with 24 mA sink capability. - TTL level input pin,5V tolerance. - TTL level input pin and schmitt trigger. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. 6.1 Power Pin Pin No. 1 11 25 37 38 39 48 Pin Name VCC GND VSB VBAT 5VSB AGND(D-) AVSB Type P P P P P P P Description Power supply voltage input with 3.3V (OVP function default is disabled). Digital GND Stand-by power supply voltage input 3.3V Battery voltage input 5V stand by power input Analog GND Analog Stand-by power supply voltage input 3.3V 6.2 2 3 4 LPC Interface Pin Name LRESET# SERIRQ LFRAM# Type INts I/O12t INts PWR VCC VCC VCC Description Reset signal. It can connect to PCIRST# signal on the host. Serial IRQ input/Output. Internal pull high 47k ohms. Indicates start of a new cycle or termination of a 10 Aug, 2010 V0.21P Pin No. F71808E 8-5 9 10 LAD[3:0] PCICLK CLKIN I/O12t INts INts VCC VCC VCC broken cycle. Internal pull high 47k ohms. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Internal pull high 47k ohms. 33MHz PCI clock input. System clock input. According to the input frequency 24/48MHz. 6.3 UART Function Pin Name DCD# Type INts5v VCC GPIO00 RI# I/OOD12ts5v Pin No. 53 PWR INts5v AVSB I/OOD12ts5v 54 GPIO01 CTS# 55 GPIO02 INts5v I/OOD12ts5v VCC DTR# O8-u47,5v Description Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. General purpose IO. GPIO function selected by register setting. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. General purpose IO. GPIO function selected by register setting. Clear To Send is the modem control input. General purpose IO. GPIO function selected by register setting. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. General purpose IO. GPIO function selected by register setting. Power on strapping pin: 1(Default): (Internal pull high) Power on fan speed default duty is 40%.(PWM) The value can be programmed and register power by VSB3V. 0: (External pull down) Power on fan speed default duty is 100%.(PWM) UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. General purpose IO. GPIO function selected by register setting. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General purpose IO. GPIO function selected by register setting. GPIO03 56 I/OOD12ts5v VCC FAN40_100 INt5v RTS# 57 GPIO04 DSR# 58 GPIO05 O8-u47,5v VCC I/OOD12ts5v INts5v VCC I/OOD12ts5v 11 Aug, 2010 V0.21P F71808E SOUT GPIO06 O8-u47,5v I/OOD12ts5v 59 VCC UART Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. General purpose IO. GPIO function selected by register setting. Power on strapping: 1(Default)Configuration register:4E 0 Configuration register:2E Serial Input. Used to receive serial data through the communication link. General purpose IO. GPIO function selected by register setting. Config4E_2E INt5v SIN 60 GPIO07 INts5v VCC I/OOD12ts5v 6.4 Hardware Monitor Pin Name D2+ D1+ VREF VIN5 VIN4 VDIMM VIN3 Type AIN AIN AOUT AIN AIN Pin No. 40 41 42 43 44 45 PWR AVSB AVSB AVSB AVSB AVSB AVSB AIN 46 47 61 62 63 VLDT VIN2 Vcore CPUFANIN CPUFANOUT SYSFANIN1 SYSFANOUT1 Description Thermal diode/transistor temperature sensor input2. Thermal diode/transistor temperature sensor input1. This pin is for CPU use. Voltage sensor output. Power down by VCC. Voltage Input. This pin supports over voltage protection function (OVP function default is disable). Voltage Input. This pin supports over voltage protection (OVP function default is disable). Voltage Input for VDIMM DUAL STR (2.5V/1.8V). 0.9V power ok. Voltage Input 3. Voltage Input for VLDT (1.2V). 0.9V power ok. Voltage Input 2. Voltage Input for Vcore. 0.6V power ok. CPU Fan tachometer input. CPU Fan control output. This pin provides PWM duty-cycle output. 40% or 100% fan speed is optioned by pin 56 power on strapping. System Fan 1 tachometer input. System Fan 1 control output. This pin provides PWM duty-cycle output or a voltage output. Pull up 4.7K to VCC to for PWM mode option. 40% or 100% fan speed is optioned by pin 56 power on strapping. General purpose IO. Intel PECI hardware monitor interface. AIN AIN INt s 5 v OD12-5v AVSB AVSB VCC VCC VCC INt s 5 v OD12-5v AOUT I/OOD12ts5v I/Os1D8tslv 64 VCC GPIO34 PECI 51 GPIO32 52 PECI_REQ VCC I/OOD12t ts5v OD12 General purpose IO. GPIO function selected by register setting. PECI request pin. VCC 12 Aug, 2010 V0.21P F71808E GPIO33 I/OOD12t ts5v General purpose IO. GPIO function selected by register setting. 6.5 ACPI Function Pins Pin Name Type PWR Description Switch 3VSB power to memory when in S3 state In S0# ( Low level In S3# ( Drive high In S5# ( Default is Low level, and can be programmed to drive high Connect to reset button. Internal with de-bounce circuit which is at least 50ms. Pull-high 10Kohm to VSB3V internally. General purpose IO. Support High/Low/Pulse/Level selection. GPIO function selected by register setting. It is an output buffer of LRESET#. This pin supports software reset by program. It is an output buffer of LRESET#. This pin supports software reset by program. S5# signal input. Internal pull high 10k ohms to VSB3V. Main power switch button input. General purpose IO. Support High/Low/Pulse/Level selection. GPIO function selected by register setting. Panel Switch Output. This pin is low active and pulse output. It is power on request output#. General purpose IO. GPIO function selected by register setting. S3# Input is Main power on-off switch input. Internal pull high 10k ohms to VSB3V Power supply on-off control output. Connect to ATX power supply PS_ON# signal. PWROK function, It is power good signal of VCC, which is delayed 400ms (default) as VCC arrives at 2.8V. Resume Reset# function, It is power good signal of VSB, which is delayed 66ms as VSB arrives at 2.3V. Internal pull high 10k ohms to VSB3V Active high. The function of this pin is to enable the PWM for CPU Vcore. The external pull high resistor is required. Active high. The function of this pin is to enable the VLDT voltage. The external pull high resistor is required. Pin No. 24 3VSBSW# O12 VSB RESETCON# 27 GPIO26 28 29 30 31 RESETOUT1# RESETOUT2# SLP_S5# PSIN# GPIO27 PSOUT# 32 GPIO14 33 34 35 SLP_S3# PSON# PWROK INts5v VSB I/OOD12t ts5v OD12 O24 INts5v INts5v I/OOD12t ts5v OD12 VSB VSB VSB VSB VSB I/OOD12t ts5v INts5v OD12-5v VSB VSB VBAT OD12 36 RSMRST# OD12 VBAT 49 VCORE_EN OD12 AVSB AVSB 50 VLDT_EN OD12 13 Aug, 2010 V0.21P F71808E 6.6 12 13 14 KBC Function Pin Name KBRST# GA20 KDAT GPIO10 KCLK Type OD16-u10,5v OD16-u10,5v I/OD16t,5v I/OOD12ts5v Pin No. PWR VCC VCC VSB I/OD16t,5v I/OOD12ts5v 15 GPIO11 MDAT VSB I/OD16t,5v I/OOD12ts5v 16 GPIO12 MCLK VSB I/OD16t,5v I/OOD12ts5v 17 GPIO13 VSB Description Keyboard reset. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P20) Gate A20 output. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P21) Keyboard Data. General purpose IO. GPIO function selected by register setting. Keyboard Clock. General purpose IO. GPIO function selected by register setting. PS2 Mouse Data. General purpose IO. GPIO function selected by register setting. PS2 Mouse Clock. General purpose IO. GPIO function selected by register setting. 6.7 Others Pin Name GPIO20 Type I/OOD12ts5v Pin No. PWR 18 PME# OD12-5v VSB GPIO21 OVT# 19 SYSFANIN2 EVENT_IN# GPIO22 I/OOD12ts5v OD12-5v VSB INt s 5 v INt s 5 v I/OOD12ts5v Description General purpose IO. Support High/Low/Pulse/Level selection. Generated PME event. It supports the PCI PME# nterface. This signal allows the peripheral to request the system to wake up from the S3 state. General purpose IO. Support High/Low/Pulse/Level selection. Over temperature signal output. OVT# function selected by register setting. System Fan 2 tachometer input. SYSFANIN2 function selected by register setting. Wake-up event input. The signal input wakes the system up from the sleep state. General purpose IO. Support High/Low/Pulse/Level selection. System Fan 2 control output. This pin provides PWM duty-cycle output or a voltage output. Pull up 4.7K to VCC to for PWM mode option. 40% or 100% fan speed is optioned by pin 56 power on strapping. The PWM Frequency can be programmed to 23.5K or 220Hz. Standby power rail control pin 1. This pin controls an external PMOS to turn on or off the standby power rail. In the S5 state, the default is set to 1 to cut off the standby power rail. General purpose pin. Support High/Low/Pulse/Level selection. 14 Aug, 2010 V0.21P SYSFANOUT2 20 OD12-5v AOUT VSB CTRL1# OD12 21 GPIO23 I/OOD12ts5v VSB F71808E WDTRST# SYSFANIN2 GPIO24 22 LEDVSB GPIO25 23 LEDVCC OD12-5v OD12-5v I/OOD12ts5v OD12-5v INt s 5 v I/OOD12ts5v Watch dog timer signal output. WDTRST# function selected by register setting. System Fan 2 tachometer input. SYSFANIN2 function selected by register setting. General purpose pin. Support High/Low/Pulse/Level selection. Power LED for VSB. Blink frequency selection. LEDVSB function selected by register setting. General purpose pin. Support High/Low/Pulse/Level selection. Power LED for VCC. Blink frequency selection. LEDVCC function selected by register setting. Standby power rail control pin 0. This pin controls an external PMOS to turn on or off the standby power rail. In the S5 state, the default is set to 1 to cut off the standby power rail. VSB VSB 26 CTRL0# OD12 VSB 15 Aug, 2010 V0.21P F71808E 7. Function Description 7.1 Power on Strapping Option The F71808E provides four pins for power on hardware strapping to select functions. There is a form to describe how to set the functions you want. Table1. Power on trap configuration Pin No. 56 59 Symbol FAN_40_100 Config4E_2E Value 1 0 1 0 Description FAN power on speed is the last programmed value. FAN power on speed is 100%. Configuration Register I/O port is 4E. (Default) Configuration Register I/O port is 2E. 7.2 Keyboard Controller The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and can be used with IBM(R)-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H. Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is "0". Status Register The status register is an 8-bit read-only register at I/O address 64H, that holds information about the status of the keyboard controller and interface. It may be read at any time. 16 Aug, 2010 V0.21P F71808E Bit 0 1 2 3 4 5 6 7 Bit Function Output Buffer Full Input Buffer Full System Flag Command/Data Inhibit Switch Mouse Output Buffer General Purpose Time-out Parity Error 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (KCCB). It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Muse output buffer empty 1: Mouse output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) Description Commands Command 20h Read Command Byte Write Command Byte BIT 0 1 2 60h 3 4 5 6 7 A7h A8h DESCRIPTION Enable Keyboard Interrupt Enable Mouse Interrupt System flag Reserve Disable Keyboard Interface Disable Mouse interface IBM keyboard Translate Mode Reserve Fucntion Disable Auxiliary Device Interface Enable Auxiliary Device Interface Auxiliary Interface Test 8'h00: indicate Auxiliary interface is ok. 8'h01: indicate Auxiliary clock is low. 8'h02: indicate Auxiliary clock is high 8'h03: indicate Auxiliary data is low 8'h04: indicate Auxiliary data is high A9h 17 Aug, 2010 V0.21P F71808E AAh Self-test Returns 055h if self test succeeds keyboard Interface Test 8'h00: indicate keyboard 8'h01: indicate keyboard 8'h02: indicate keyboard 8'h03: indicate keyboard 8'h04: indicate keyboard interface is ok. clock is low. clock is high data is low data is high ABh ADh AEh C0h C1h C2h CAh CBh D0h D1h D2h D3h D4h FEh Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Read the data written by CBh command. Written a scratch data. This byte could be read by CAh command. Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Muse Output next received byte of data from system to Mouse Pulse only RC(the reset line) low for 6S if Command byte is even KBC Command Description PS2 wakeup function The KBC supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational key (1) CTRL +ESC (2) CTRL+F1 (3) CTRL+ User Defined Code (4) ANY KEY (5) windows 98 wakeup up key (6) windows 98 power key (7) CTRL + ALT + User Defined Code (8) User Defined Code, KBC will assert PME signal. Mouse wakeup function has 2 kinds of conditions, when mouse (1) BUTTON CLICK or (2) BUTTON CLICK AND MOVEMENT, KBC will assert PME signal. Those wakeup conditions are controlled by configuration register. 7.3 Hardware Monitor For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.048V. Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these analog inputs. The voltage higher than 2.048V should be reduced by a factor with external resistors so as to obtain the input range. Only 3VCC/VSB/VBAT is an exception for it is main power of the F71808E. Therefore 3VCC/VSB/VBAT can directly connect to this chip's power pin and need no external resistors. There 18 Aug, 2010 V0.21P F71808E are two functions in this pin with 3.3V. The first function is to supply internal analog power of the F71808E and the second function is that voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V. There are five voltage inputs in the F71808E and the voltage divided formula is shown as follows: VIN = V+12V x R2 R1 + R2 where V+12V is the analog input voltage, for example. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the tolerance. As for application circuit, it can be refer to the figure shown as follows. 3VCC/VSB Voltage Inputs VIN (Lower than 2.048V) VIN(Higher than 2.048V) (directly connect to the chip) (directly connect to the chip) VIN1(Max2.048V) R1 R2 150K VIN3.3 150K VREF R 10K, 1% D+ Typical BJT Connection 2N3906 Typical Thermister Connection RTHM 10K, 25 C D- 8-bit ADC with 8 mV LSB Figure 2. Hardware monitor configuration The F71808E monitors two remote temperature sensors.These sensors can be measured from -40C to 127C. More details, please refer register description. Table 2. Remote-sensor transistor manufacturers Manufacturer Panasonic Philips Model Number 2SB0709 2N3906 PMBT3906 Table Range: 19 Aug, 2010 V0.21P F71808E Table 3. Display range is from -40C to 127C in 2's complement format. Temperature -40C -1C 1C 90C 127C Open Digital Output 1101 1000 1111 1111 0000 0001 0101 1010 1111 1111 1000 0000 Monitor Temperature from "Thermistor" The F71808E can connect three thermistors to measure environment temperature or remote temperature. The specification of thermistor should be considered to (1) value is 3435K (2) resistor value is 10K ohm at 25C. In the Figure 6-1, the thermistor is connected by a serial resistor with 10K ohm, and then connected to VREF. The temperature measurement range is 0~127C. Monitor Temperature from "Thermal diode" Also, if the CPU, GPU or external circuits provide thermal diode for temperature measurement, the F71808E is capable to these situations. The build-in reference table is for PNP 2N3906 transistor. In the Figure 7-1, the transistor is directly connected into temperature pins. ADC Noise Filtering The ADC is integrating type with inherently good noise rejection. Micro-power operation places constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF capacitor. Too high capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurement to be higher than the actual temperature, depending on the frequency and amplitude. Monitor Temperature from "PECI" F71808E support Intel PECI1.1/PECI_Request interfaces to read temperature from PECI 1.1 device. Temperature HM_IRQ Signal (HM_IRQ# and PME#) Over temperature event will trigger HM_IRQ# that shown as figure. When monitored temperature exceeds the high temperature threshold value, HM_IRQ# will be asserted until the 20 Aug, 2010 V0.21P F71808E temperature goes below the hysteresis temperature. T High T HYST HM_IRQ# Figure 3 PME# interrupt for temperature is shown as figure. Temperature exceeding high limit (low limit) or going below high hysteresis (low hysteresis) will cause an interrupt if the previous interrupt has been reset by writing "1" all the interrupt Status Register. T HIGH T Hhys T LOW T Lhys PME# (pulse mode) * * * * *Interrupt Reset when Interrupt Status Registers are written 1 Figure 4 Hysteresis mode illustration Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. Determine the fan counter according to: Count = 1.5 x 10 6 RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by 21 Aug, 2010 V0.21P F71808E the following equation. As for fan, it would be best to use 2 pulses tachometer output per round. RPM = 1.5 x 10 6 Count Fan speed control The F71808E provides 2 fan speed control methods: 1. DAC FAN CONTROL 2. PWM DUTY CYCLE DAC Fan Control The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Output_voltage (V) = 3.3 x Programmed 8bit Register Value 255 And the suggested application circuit for linear fan control would be: 12V 3 DC OUTPUT VOLTAGE 2 8 + 4 1 LM358 PMOS D1 1N4148 R 4.7K JP1 R 10K C 47u 3 2 1 CON3 R 27K FANIN MONITOR C 0.1u R 10K R 3.9K DC FAN Control with OP Figure 5 DAC fan control application circuit PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8bit Register Value x 100% 255 22 Aug, 2010 V0.21P F71808E +12V R1 R2 D G NMOS S + C FAN PNP Transistor Figure 6 +12/5V PWM fan control application circuit Fan speed control mechanism There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode 3. Linear auto mode. More detail, please refer the description of registers. Each fan can be controlled by up to 7 kinds of temperature input. (1)D1+ temperature (2)D2+ temperature (3) PECI temperature. Please refer below structure diagram. PECI Expect speed1 Fan1 D1+ T (T1) Expect speed 2 Fan2 D2+ T (T2) Expect speed 3 Fan3 [ Figure 7 Relative temperature fan control 23 Aug, 2010 V0.21P F71808E Manual mode For manual mode, it generally acts as software fan speed control. Stage auto mode At this mode, the F71808E provides automatic fan speed control related to temperature variation of CPU/GPU or the system. The F71808E can provide two temperature boundaries and three intervals, and each interval has its related fan speed PWM duty. All these values should be set by BIOS first. Take figure 6-10 as example. When temperature boundaries are set as 45 and 75(C and there are three intervals. The related desired fan speed for each interval are 40%, 80% and 100% (fixed). When the temperature is within 45~75'C, the fan speed will follow 80% PWM duty and that define in registers. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature variation. The F71808E will take charge of all the fan speed control and need no software support. Temperature PWM Duty 100% 75 Degree C 80% 45 Degree C 40% Temperature Fan Speed Figure 8 Stage mode fan control illustration-1 Below is a sample for Stage auto mode: Set temperature as 60C, 40C and Duty as 100%, 70%, 50% PWM duty 100% 60 Degree C hysteresis 57 Degree C 40 Degree C 50% 70% Temp. Fan Speed a b c d Figure 9 Stage mode fan control illustration-2 a. Once temp. is under 40C, the lowest fan speed keeps 50% PWM duty b. Once temp. is over 40C,60C, the fan speed will vary from 70% to 100% PWM duty and increase 24 Aug, 2010 V0.21P F71808E with temp. level. c. Once temp. keeps in 55C, fan speed keeps in 70% PWM duty 70% PWM duty and stays there. d. If set the hysteresis as 3C (default 4C), once temp reduces under 57C, fan speed reduces to Linear auto mode Otherwise, F71863 supports linear auto mode. Below has a example to describe this mode. More detail, please refer the register description. A. Linear auto mode (PWM Duty I) Set temperature as 70C, 40C and Duty as 100%, 70%, 40% PWM duty 70 Degree C hysteresis 65 Degree C 100% 70% 40 Degree C Temp. Fan Speed 40% a b c d Figure 10 Linear mode fan control illustration a. Once temp. is under 40C, the lowest fan speed keeps 40% PWM duty b. Once temp. is over 40C and under 70C, the fan speed will vary from 40% to 70% PWM duty and linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec. c. Once temp. goes over 70C, fan speed will directly increase to 100% PWM duty (full speed) reduces from 100% PWM duty and decrease linearly with temp.. d. If set the hysteresis as 5C(default is 4C), once temp reduces under 65C (not 70C), fan speed 7.4 ACPI Function The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer's power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. S5 is a state that memory is off and the last procedural state of the processor has been stored 25 Aug, 2010 V0.21P F71808E to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. It is anticipated that only the following state transitions may happen: S0S3, S0S5, S5S0, S3S0 and S3S5. Among them, S3S5 is illegal transition and won't be allowed by state machine. It is necessary to enter S0 first in order to get to S5 from S3. As for transition S5S3 will occur only as an immediate state during state transition from S5S0. It isn't allowed in the normal state transition. The below diagram described the timing, the always on and always off, keep last state could be set in control register. In keep last state mode, one register will keep the status of before power loss. If it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V Figure 11 Default timing: Always off 26 Aug, 2010 V0.21P F71808E VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V Figure 12 Optional timing: Always on Figure 13 AMD power sequence 3VSBSW# Timing The 3VSBSW# is used to switch the power source of the 5VDUAL which is combined by the 5VCC and 5VSB rails according to the ACPI state to control the power rail of the DIMM especially. The timing charts of the every ACPI state are mentioned in the following figures. 27 Aug, 2010 V0.21P F71808E Figure 14 3VSBSW# Timing: S5 S0 Figure 15 3VSBSW# Timing: S0 S3 28 Aug, 2010 V0.21P F71808E Figure 16 3VSBSW# Timing: S3 S0 Figure 17 3VSBSW# Timing: S0 S5 PCI Reset and PWROK Signals The F71808E supports 2 output buffers for 2 reset signals. 29 Aug, 2010 V0.21P F71808E +3.3V Delay PWROK LRESET# Buffer PCIRST1~2# RSTCON# So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as VCC arrives 2.8V, and the delay timing can be programmed by register (100ms ~ 400ms). An additional delay could be added to PWROK (0ms, 100ms, 200ms and 400ms). Default is 0ms. RSTCON# could be programmed to be asserted via PWROK. 7.5 INTEL PECI Function The F71808E provides Intel PECI interface for new generational CPU temperature sensing. In Intel PECI interface, the F71808E can connect to CPU directly. The F71808E can read the temperature data from CPU, than the fan control machine of F71808E can implement the Fan to cool down CPU temperature. The application circuit is as below. More detail please refer to the register description. Intel CPU PECI avoid pre-BIOS floating F71808E PECI 100K Figure 19 INTEL PECI typical application 7.6 Over Voltage Protection The F71808E supports Over Voltage Protection (abbreviated in OVP in the following paragraph) function to avoid that the system is damaged by the higher voltage than the expected. The hardware monitors, VIN0, VIN4, and VIN5, monitor the input voltages which exceed the settings (CR31h, 35h, 36h) if OVP function is enabled (CR10h). OVP function is disabled in the default setting. 7.7 Power Saving Controller The two pins, CTRL0# and CTRL1#, which control the standby power rail on/off to fulfil the purpose which decreases the power consumption when the system in the sleep state or the soft-off state. These two pins connected to the external PMOSs and the defaults are high in the sleep state in order to cut off all the standby power rails to save the power consumption. If the system needs to support wake-up function, the two 30 Aug, 2010 V0.21P F71808E pins can be programmable to set which power rail is turned on. The programmable register is powered by battery. So, the setting is kept even the AC power is lost when the register is set. At the power saving state (FINTEK calls it G3-like state), the F71808E consumes 5VSB power rail only to realize a low power consumption system. 31 Aug, 2010 V0.21P F71808E 8. Register Description The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 -o 4e aa ( enable configuration ) ( disable configuration ) The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. Please refer each device chapter if you want more detail information. Global Control Registers "-" Reserved or Tri-State Global Control Registers Register 0x[HEX] 02 07 20 21 23 24 25 26 27 29 2A 2B 2C 2D Register Name Software Reset Register Logic Device Number Register (LDN) Chip ID Register Chip ID Register Vendor ID Register Vendor ID Register Software Power Down Register Clock Select Register Configuration Port Select Register Multi-function Select Register1 Multi-function Select Register2 Multi-function Select Register3 VBAT Dummy Register Wakeup Control Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 LSB 0 0 1 1 1 0 1 0 0 1 0 0 32 Aug, 2010 V0.21P F71808E 2E 2F Reserved Reserved - Device Configuration Registers "-" Reserved or Tri-State UART Device Configuration Registers (LDN CR01) Register 0x[HEX] 30 60 61 70 F0 Register Name UART Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register RS485 Enable Register Default Value MSB 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 1 0 0 LSB 1 1 0 0 - Hardware Monitor Device Configuration Registers (LDN CR04) Register 0x[HEX] 30 60 61 70 Register Name H/W Monitor Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Default Value MSB 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 LSB 1 0 1 0 KBC Device Configuration Registers (LDN CR05) Register 0x[HEX] 30 60 61 70 72 FE FF Register Name KBC Device Enable Register Base Address High Register Base Address Low Register KB IRQ Channel Select Register Mouse IRQ Channel Select Register Swap Register User Wakeup Code Register Default Value MSB 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 LSB 1 0 0 1 0 1 1 GPIO Device Configuration Registers (LDN CR06) Register 0x[HEX] 70 C0 C1 C2 C3 Register Name GPIRQ Channel Select Register GPIO3 Output Enable Register GPIO3 Output Data Register GPIO3 Pin Status Register GPIO3 Drive Enable Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 LSB 0 0 1 0 33 Aug, 2010 V0.21P F71808E D0 D1 D2 D3 D4 D5 D6 D7 D8 E0 E1 E2 E3 F0 F1 F2 F3 GPIO2 Output Enable Register GPIO2 Output Data Register GPIO2 Pin Status Register GPIO2 Drive Enable Register GPIO2 PME Enable Register GPIO2 Detect Edge Select Register GPIO2 PME Status Register GPIO2 Outpute Mode Select Register GPIO2 Pulse Width Select Register GPIO1 Output Enable Register GPIO1 Output Data Register GPIO1 Pin Status Register GPIO1 Drive Enable Register GPIO Output Enable Register GPIO Output Data Register GPIO Pin Status Register GPIO Drive Enable Register 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 WDT Device Configuration Registers (LDN CR07) Register 0x[HEX] 30 60 61 F0 F2 F3 F4 F5 F6 F7 Register Name WDT Device Enable Register Base Address High Register Base Address Low Register WDTRST# Output Enable Register Reserved Rserved Reserved WDT Unit Select Register WDT Count Register Watchdog Timer PME Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 LSB 0 0 0 1 0 0 - PME, ACPI, Power Saving Device Configuration Registers (LDN CR0A) Register 0x[HEX] 30 F0 F1 F2 F3 Register Name PME Device Enable Register PME Event Enable Register 1 PME Event Status Register 1 PME Event Enable Register 2 PME Event Status Register 2 Default Value MSB 0 0 0 0 0 0 LSB 0 0 - 34 Aug, 2010 V0.21P F71808E F4 F5 F6 F7 F8 F9 FE Keep Last State Select Register VDDOK Delay Select Register PCIRST Control Register VSBGATE Control Register LED VCC Control Register LED VSB Control Register RI De-bounce Select Register 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 8.1 8.1.1 Bit 7-1 0 8.1.2 Bit Global Control Registers Software Reset Register Index 02h Name Reserved SOFT_RST R/W Default R/W 0 Reserved Write 1 to reset the register and device powered by VDD (VCC ). Description Logic Device Number Register (LDN) Index 07h Name R/W Default Description 01h: Select UART device configuration registers. 04h: Select Hardware Monitor device configuration registers. 05h: Select KBC device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME, ACPI & Power Saving device configuration registers. 7-0 LDN R/W 00h 8.1.3 Bit 7-0 8.1.4 Bit 7-0 8.1.5 Bit 7-0 Chip ID Register Index 20h Name CHIP_ID1 R/W Default R 09h Chip ID 1. Description Chip ID Register Index 21h Name CHIP_ID2 R/W Default R 01h Chip ID2. Description Vendor ID Register Index 23h Name VENDOR_ID1 R/W Default R 19h Description Vendor ID 1 of Fintek devices. 35 Aug, 2010 V0.21P F71808E 8.1.6 Bit 7-0 8.1.7 Bit 7-2 1 0 Vendor ID Register Index 24h Name VENDOR_ID2 R/W Default R 34h Description Vendor ID 2 of Fintek devices. Software Power Down Register Index 25h Name Reserved SOFTPD_UR Reserved R/W Default R/W 0 Reserved. Write "1" to disable UART clock. Reserved. Description 8.1.8 Bit 7 6-3 2 1-0 UART IRQ Sharing Register Index 26h Name CLK24M_SEL Reserved TX_DEL_1BIT Reserved R/W Default R/W R/W 0 0 0: CLKIN is 48MHz 1: CLKIN is 24MHz Reserved. 0: UART TX transmits data immediately after writing THR. 1: UART TX transmits data one bit time after writing THR. Reserved. Description 8.1.9 Bit 7-5 Configuration Port Select Register Index 27h Name Reserved R/W Default Reserved. 0: The configuration register port is 2E/2F. Description 4 PORT_4E_EN R/W - 1: The configuration register port is 4E/4F. This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select port 2E/2F. 3-1 0 Reserved TIMING_EN R/W 1 Reserved. 0: Disable timing sequence. 1: Enable timing sequence. 8.1.10 Bit Multi-Function Select Register 1 Index 29h (Powered by VSB3V) Name R/W Default Description 36 Aug, 2010 V0.21P F71808E UART/GPIO function select. 00 : All Pins for UART 7-6 UR_GP_EN R/W 0 01: SIN/SOUT enable, other pins are GPIOs. 10: SIN/SOUT/RTS# enable, other pins are GPIOs. 11: All pins are GPIOs. 5 Reserved Reserved SYSFANOUT/GPIO34 function select. 4 GPIO34_EN R/W 0 0: The pin function is SYSFANOUT. 1: The pin function is GPIO34. 3-2 Reserved Reserved VLDT_EN/GPIO31 function select. 1 GPIO31_EN R/W 0 0: The pin function is VLDT_EN 1: The pin function is GPIO31 VCORE_EN/GPIO34 function select. 0 GPIO30_EN R/W 0 0: The pin function is VCORE_EN 1: The pin function is GPIO30 Multi-Function Select Register 2 Index 2Ah (Powered by VSB3V) Name Reserved R/W Default Reserved PSOUT#/GPIO14 function select. 4 PSOUT_GP_EN R/W 0 0: The pin function is PSOUT#. 1: The pin function is GPIO14. GPIO23/WDTRST#/SYSFANIN2 function select. 3 FANIN2_GP23_EN R/W 0 0: The pin function is GPIO23/WDTRST#. 1: The pin function is FANIN2 GPIO21/OVT#/SYSFANIN2 function select. 0: The pin function is GPIO21/OVT#. 2 FANIN2_GP21_EN R/W 0 1: The pin function is FANIN2. The priority of FANIN3_GP23_EN is higher than FANIN3_GP21_EN. Description 8.1.11 Bit 7-5 37 Aug, 2010 V0.21P F71808E KBC/GPIO function select. 0: The pin function of pin 14 and 15 are KDATA and KCLK 1 KB_GP_EN R/W 0 respectively. 1: The pin function of pin 14 and 15 are GPIO10 and GPIO11 respectively. KBC/GPIO function select. 0: The pin function of pin 16 and 17 are MDATA and MCLK 0 MO_GP_EN R/W 0 respectively. 1: The pin function of pin 16 and 17 are GPIO12 and GPIO13 respectively. Multi-Function Select Register 3 Index 2Bh (Powered by VSB3V) Name R/W Default Description PSIN#/GPIO27 function select. 7 GPIO27_EN R/W 0 0: The pin function is PSIN#. 1: The pin function is GPIO27. RESETCON#/GPIO26 function select. 6 GPIO26_EN R/W 0 0: The pin function is RESETCON#. 1: The pin function is GPIO26. GPIO25/LEDVCC function select. 5 GPIO25_EN R/W 1 0: The pin function is LEDVCC. 1: The pin function is GPIO25. GPIO24/LEDVSB function select. 4 GPIO24_EN R/W 1 0: The pin function is LEDVSB. 1: The pin function is GPIO24. GPIO23/WDTRST#/SYSFANIN2 function select. 3 GPIO23_EN R/W 1 0: The pin function is WDTRST#. 1: The pin function is GPIO23. This bit has effect only if FANIN3_GP23_EN is "0". GPIO22/SYSFANOUT2 function select. 2 GPIO22_EN R/W 1 0: The pin function is SYSFANOUT2. 1: The pin function is GPIO22. 8.1.12 Bit 38 Aug, 2010 V0.21P F71808E GPIO21/OVT#/SYSFANIN2 function select. 1 GPIO21_EN R/W 1 0: The pin function is OVT#. 1: The pin function is GPIO21. This bit has effect only if FANIN3_GP21_EN is "0". GPIO20/PME# function select. 0 GPIO20_EN R/W 1 0: The pin function is PME#. 1: The pin function is GPIO20. Wakeup Control Register Index 2Dh (Powered by VBAT) Name Reserved R/W Default 0 Reserved 0: Enable VSBOK detect hysteresis. 1: Disable VSBOK detect hysteresys. 0: VSB3V power good level is 3.05V and not good level is 2.95V. 1: VSB3V power good level is 2.8V and not good level is 2.5V. By VSBOK_HYS_DIS and VSBOK_LVL_SEL, RSMRST# falling 5 VSBOK_LVL_SEL R/W 1 edge could be determined: 00: when VSB3V is lower than 2.95V. 01: when VSB3V is lower than 2.5V. 10: when VSB3V is lower than 3.05V. 11: when VSB3V is lower than 2.8V. 4 3 KEY_SEL_ADD WAKEUP_EN R/W R/W 0 1 This bit is added to add more wakeup key function. 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. Description 8.1.13 Bit 7 6 VSBOK_HYS_DIS R/W 39 Aug, 2010 V0.21P F71808E This registers select the keyboard wake up key. Accompanying with KEY_SEL_ADD, there are eight wakeup keys: KEY_S EL_AD D 0 0 2-1 KEY_SEL R/W 00 0 0 1 1 1 1 KEY _SEL 00 01 10 11 00 01 10 11 Ctrl + Esc Ctrl + F1 Ctrl + USER_WAKEUP_CODE (SPACE) Any Key Windows Wakeup Windows Power Ctrl + Alt + USER_WAKEUP_CODE (SPACE) USER_WAKEUP_CODE (SPACE) Wakeup Key This register select the mouse wake up key. 0 MO_SEL R/W 0 0: Wake up by click. 1: Wake up by click and movement. 8.2 8.2.1 Bit 7-1 0 UART Registers (CR01) UART 1 Device Enable Register Index 30h Name Reserved UR_EN R/W Default R/W 1 Reserved 0: disable UART. 1: enable UART. Description 8.2.2 Bit 7-0 Base Address High Register Index 60h Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of UART base address. 40 Aug, 2010 V0.21P F71808E 8.2.3 Bit 7-0 8.2.4 Bit 7-4 3-0 8.2.5 Bit 7-6 5 4 RS485_EN R/W 0 Base Address Low Register Index 61h Name R/W Default F8h Description The LSB of UART base address. BASE_ADDR_LO R/W IRQ Channel Select Register Index 70h Name Reserved SELURIRQ R/W Default R/W 4h Reserved. Select the IRQ channel for UART. Description RS485 Enable Register Index F0h Name Reserved RS485_INV R/W Default Reserved. Write "1" will invert the RTS# if RS485_EN is set. 0: RS232 driver. 1: RS485 driver. RTS# drive high when transmitting data, otherwise is kept low. Description 3-0 Reserved - - Reserved. 8.3 8.3.1 Hardware Monitor Register (CR04) Hardware Monitor Configuration Registers Hardware Monitor Device Enable Register Index 30h Bit 7-1 0 Name Reserved HM_EN R/W Default R/W 1 Reserved 0: disable Hardware Monitor. 1: enable Hardware Monitor. Description Base Address High Register Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 02h Description The MSB of Hardware Monitor base address. Base Address Low Register Index 61h Bit Name R/W Default Description 41 Aug, 2010 V0.21P F71808E 7-0 BASE_ADDR_LO R/W 95h The LSB of Hardware Monitor base address. IRQ Channel Select Register Index 70h Bit 7-4 3-0 8.3.2 Name Reserved SELHMIRQ Device Registers R/W Default R/W 0000 Reserved. Select the IRQ channel for Hardware Monitor. Description Before the device registers, the following is a register map order which shows a summary of all registers. Please refer each one register if you want more detail information. Register CR01 ~ CR03 Register CR0A ~ CR0F Register CR10 ~ CR4F Register CR60 ~ CR8E Register CR90 ~ CRDF Configuration Registers PECI/SST Control Register Voltage Setting Register Temperature Setting Register Fan Control Setting Register Fan1 Detail Setting CRA0 ~ CRAF Fan2 Detail Setting CRB0 ~ CRBF Fan3 Detail Setting CRC0 ~ CRCF Fan4 Detail Setting CRD0 ~ CRDF Configuration Register Index 01h Bit 7-3 2 1 Name Reserved POWER_DOWN FAN_START R/W Default R/W R/W 0 1 Reserved Hardware monitor function power down. Set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. Set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. Description 0 V_T_START R/W 1 Configuration Register Index 02h Bit 7 6 5-4 3-0 Name Reserved Reserved OVT_MODE Reserved R/W Default R/W 0 Reserved Reserved 00: The OVT# will be low active level mode. 01: The OVT# will be high active level mode. 10: The OVT# will indicate by 1Hz LED function. 11: The OVT# will indicate by (400/800HZ) BEEP output. Reserved Description 42 Aug, 2010 V0.21P F71808E Configuration Register Index 03h Bit 7-0 Name Reserved R/W Default Reserved Description Configuration Register Index 0Ah Bit 7-4 Name Reserved R/W Default Reserved. PECI (Vtt) voltage select. 00: Vtt is 1.23V 3-2 VTT_SEL R/W 0 01: Vtt is 1.13V 10: Vtt is 1.00V 11: Vtt is 1.00V Function select bits to select PECI function. 00: Disable PECI Function 1-0 FUNC_SEL R/W 0 01: Reserved 10: Enable PECI Function 11: Reserved Description Configuration Register Index 0Bh Bit Name R/W Default Description Select the Intel CPU socket number. 0000: no CPU presented. PECI host will use Ping() command to find CPU address. 7-4 CPU_SEL R/W 0 0001: CPU is in socket 0, i.e. PECI address is 0x30. 0010: CPU is in socket 1, i.e. PECI address is 0x31. 0100: CPU is in socket 2, i.e. PECI address is 0x32. 1000: CPU is in socket 3, i.e. PECI address is 0x33. Otherwise are reserved. 3-1 0 Reserved DOMAIN1_EN R/W 0 Reserved. If the CPU selected is dual core. Set this register 1 to read the temperature of domain1. Configuration Register Index 0Ch Bit Name R/W Default Description 43 Aug, 2010 V0.21P F71808E TCC Activation Temperature. When PECI is enabled, the absolute value of CPU temperature 7-0 TCC_TEMP R/W 55h is calculated by the equation: CPU_TEMP = TCC_TEMP + PECI Reading. The range of this register is -128 ~ 127. Configuration Register Index 0Fh Bit 7-6 5 4-2 Name Reserved PECI_REQ_EN Reserved R/W Default R/W 1 Reserved. 0: disable the PECI_REQ# function. 1: Enable the PECI_REQ# function. Reserved. The accessing rate for PECI to access external slave device. 0: Access slave device after 1 diode temperature conversion 1-0 DIG_RATE_SEL R/W 0 1: Access slave device after 2 diode temperature conversion 2: Access slave device after 3 diode temperature conversion 3: Access slave device after 4 diode temperature conversion Description - Voltage Setting Over-Voltage Shut Down Enable Register Index 10h Bit 7-6 5 Name Reserved V5_OVV_EN R/W Default R/W 0 Reserved. A one enables the shut down event when V5 is over V5_OVV_LIMIT. A one enables the shut down event when V4 is over V4_OVV_LIMIT. Reserved. A one enables the shut down event when V0 is over V0_OVV_LIMIT. Description 4 3-1 0 V4_OVV_EN Reserved V0_OVV_EN R/W R/W 0 0 Over-Voltage Status Register (Powered by VBAT) Index 11h Bit 7-6 Name Reserved R/W Default Reserved Description 44 Aug, 2010 V0.21P F71808E This bit is over-voltage status. Once one of the monitored 0 V_EXC_OVV R/W C voltages (VCC3V, VIN4, VIN5) over its related over-voltage limits 0 and its related over-voltage shut down enable bit is set, this bit will be set to 1. Write a 1 to this bit will clear it to 0. (This bit is powered by VBAT) Voltage reading and limit Index 20h- 4Fh Address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29~2Ch 2Dh 2Eh 2Fh 30h 31h 32~34h 35h 36h 37~4Fh Attribute RO RO RO RO RO RO -RO RO RO RO RO RO -R/W RO R/W R/W RO Default Value --------------FF -FF FF -Description VCC3V reading. The unit of reading is 8mV. V1 (Vcore) reading. The unit of reading is 8mV. V2 reading. The unit of reading is 8mV. V3 reading. The unit of reading is 8mV. V4 reading. The unit of reading is 8mV. V5 reading. The unit of reading is 8mV. Reserved VSB3V reading. The unit of reading is 8mV. VBAT reading. The unit of reading is 8mV. Reserved FAN1 present fan duty reading FAN2 present fan duty reading FAN3 present fan duty reading Reserved V0 over-voltage limit (V0_OVV_LIMIT). The unit is 9mv. Reserved V4 over-voltage limit (V4_OVV_LIMIT). The unit is 9mv. V5 over-voltage limit (V5_OVV_LIMIT). The unit is 9mv. Reserved Temperature Setting Temperature PME# Enable Register Index 60h Bit 7 6 Name Reserved EN_ T2_ OVT_PME R/W Default R R/W 0 Reserved If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT setting. Description 45 Aug, 2010 V0.21P F71808E 5 4 3 2 EN_ T1_ OVT_PME Reserved Reserved R/W R R 0 0 If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT setting. Reserved Reserved If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high limit setting. Reserved EN_ T2_EXC_PME R/W 1 0 EN_ T1_EXC_PME R/W Reserved R 0 - Temperature Interrupt Status Register Index 61h Bit 7 Name Reserved R/W Default Reserved A one indicates TEMP2 temperature sensor has exceeded 6 T2_OVT _STS R/W 0 OVT limit or below the "OVT limit -hysteresis". Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded 5 T1_OVT _STS R/W 0 OVT limit or below the "OVT limit -hysteresis". Write 1 to clear this bit, write 0 will be ignored. 4 3 Reserved Reserved Reserved Reserved A one indicates TEMP2 temperature sensor has exceeded 2 T2_EXC _STS R/W 0 high limit or below the "high limit -hysteresis" limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded high 1 T1_EXC _STS R/W 0 limit or below the "high limit -hysteresis" limit. Write 1 to clear this bit, write 0 will be ignored. 0 Reserved Reserved Description Temperature Real Time Status Register Index 62h Bit 7 6 Name Reserved T2_OVT R/W Default R/W 0 Reserved Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is below the "OVT limit -hysteresis" temperature. Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is below the "OVT limit -hysteresis" temperature. Description 5 T1_OVT R/W 0 46 Aug, 2010 V0.21P F71808E 4 3 2 Reserved Reserved T2_EXC R/W 0 Reserved Reserved Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is below the "high limit -hysteresis" temperature. Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is below the "high limit -hysteresis" temperature. Reserved 1 0 T1_EXC Reserved R/W - 0 - T1 Over-OVT and Over-High Limit Temperature Select Register Index 64h Bit 7-6 Name Reserved R/W Default Reserved Set this bit to select the temperature source of T1_OVT_LIMIT. 5-4 T1_OVT_TEMP_S EL 00: Diode T1 Temperature R/W 0 01: PECI Temperature 10: Reserved 11: Reserved 3-2 Reserved Reserved Set this bit to select the temperature source of T1_HIGH_LIMIT. 1-0 T1_HIGH_TEMP_ SEL 00: Diode T1 Temperature R/W 0 01: PECI Temperature 10: Reserved 11: Reserved Description OVT Output Enable Register 1 Index 66h Bit 7-3 2 1 0 Name Reserved EN_T2_OVT EN_T1_OVT Reserved R/W Default R/W R/W 0 1 Reserved Enable over temperature (OVT) mechanism of temperature2. Enable over temperature (OVT) mechanism of temperature1. Reserved. Description Temperature1 Offset Register -- Index 67-68h Bit 7-0 Name Reserved R/W Default Reserved Description Temperature Sensor Type Register Index 6Bh Bit 7-3 Name Reserved R/W Default Reserved Description 47 Aug, 2010 V0.21P F71808E 2 1 0 T2_MODE T1_MODE Reserved R/W R/W 1 1 0: TEMP2 is connected to a thermistor. 1: TEMP2 is connected to a BJT. (default) 0: TEMP1 is connected to a thermistor 1: TEMP1 is connected to a BJT.(default) Reserved TEMP1 Limit Hystersis Select Register -- Index 6Ch Bit 7-4 3-0 Name TEMP1_HYS Reserved R/W Default R/W 4h Description Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary - hysteresis ). Reserved TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh Bit 7-4 3-0 Name Reserved TEMP2_HYS R/W Default R/W 4h Reserved Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary - hysteresis ). Description DIODE OPEN Status Register -- Index 6Fh Bit 7-6 5 4-3 2 1 0 Name Reserved PECI_OPEN Reserved R/W Default RO 0h 0h 0h Reserved When PECI interface is enabled, it indicates an error code (0x0080 or 0x0081) is received from PECI slave. Reserved Set to 1 when external diode 2 is open or short Set to 1 when external diode 1 is open or short Reserved Description T2_DIODE_OPEN RO T1_DIODE_OPEN RO Reserved - Diode T1 Temperature Scale Register -- Index 7Fh Bit 7-5 Name Reserved R/W Default Reserved Diode T1 Temperature scale selection. 3 ADD R/W 0h 1: Temp. = Reading Value + Reading Value* 2 - DIODE _ T 1 _ SCALE 0: Temp. = Reading Value - Reading Value* 2 - DIODE _ T 1 _ SCALE 2 Reserved Reserved Description 48 Aug, 2010 V0.21P F71808E When ADD is 1, Diode T1 Temp. is selected by SCALE 00: Temp. = 1 * Reading Value 01: Temp. = 17/16 * Reading Value 10: Temp. = 33/32 * Reading Value 11: Temp. = 65/64 * Reading Value 1-0 SCALE R/W 0h When ADD is 0, Diode T1 Temp. is selected by SCALE 00: Temp. = 1 * Reading Value 01: Temp. = 15/16 * Reading Value 10: Temp. = 31/32 * Reading Value 11: Temp. = 63/64 * Reading Value Temperature Index 70h- 8Fh Address 70h 71h 72h 73h 74h 75h 76h 77-79h 7Eh 80h 81h 82h 83h 84h 85h 86-8Bh 8C~8Dh Attribute Reserved Reserved RO RO RO RO RO RO RO --R/W R/W R/W R/W --Default Value -----------64h 55h 64h 55h --Reserved Reserved Temperature 1 reading. The unit of reading is 1C.At the moment of reading this register. Reserved Temperature 2 reading. The unit of reading is 1C.At the moment of reading this register. Reserved Reserved Reserved The data of CPU temperature from digital interface after IIR filter. (Only available if PECI interface is enabled) Reserved Reserved Temperature sensor 1 OVT limit. The unit is 1C. Temperature sensor 1 high limit. The unit is 1C. Temperature sensor 2 OVT limit. The unit is 1C. Temperature sensor 2 high limit. The unit is 1C. Reserved Reserved Description Fan Control Setting 49 Aug, 2010 V0.21P F71808E FAN PME# Enable Register Index 90h Bit 7-3 Name Reserved R/W Default Reserved A one enables the corresponding interrupt status bit for PME# 2 EN_FAN3_PME R/W 0h interrupt.. Set this bit 1 to enable PME# function for Fan3. A one enables the corresponding interrupt status bit for PME# 1 EN_FAN2_PME R/W 0h interrupt. Set this bit 1 to enable PME# function for Fan2. A one enables the corresponding interrupt status bit for PME# 0 EN_FAN1_PME R/W 0h interrupt. Set this bit 1 to enable PME# function for Fan1. Description FAN Interrupt Status Register Index 91h Bit 7-3 2 Name Reserved FAN3_STS R/W Default R/W Reserved This bit is set when the fan3 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan2 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan1 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. Description 1 FAN2_STS R/W - 0 FAN1_STS R/W - FAN Real Time Status Register Index 92h Bit 7-3 Name Reserved R/W Default Reserved This bit set to high mean that fan3 count can't meet expect count 2 FAN3_EXC RO over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan2 count can't meet expect count 1 FAN2_EXC RO over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan1 count can't meet expect count 0 FAN1_EXC RO over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. Description 50 Aug, 2010 V0.21P F71808E FAN Full Speed Enable Register Index 93h Bit 7 6 Name Reserved FULL_WITH_T2_E N FULL_WITH_T1_E N Reserved R/W Default R/W 0 Reserved. Set one will enable FAN to force full speed when T2 over high limit. Set one will enable FAN to force full speed when T1 over high limit. Reserved. Description 5 4-0 R/W - 0 - Fan Type Select Register -- Index 94h Bit 7-6 Name Reserved R/W Default Reserved. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan's power terminal. 5-4 SYSFAN2_TYPE R/W 2'b 1S 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. Bit 0 is power on trap by SYSFAN2OUT 0: SYSFAN2OUTis pull up by external resistor. 1: SYSFAN2OUT is pull down by internal 100K resistor. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan's power terminal. 3-2 SYSFAN1_TYPE R/W 2'b 1S 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. Bit 0 is power on trap by SYSFAN1OUT 0: SYSFAN1OUT is pull up by external resistor. 1: SYSFAN1OUT is pull down by internal 100K resistor. 1-0 CPUFAN_TYPE R/W 2'b 10 00: Output PWM mode (push pull) to control fans. 10: Output PWM mode (open drain) to control Intel 4-wire fans. Description S: Register default values are decided by trapping. Fan mode Select Register -- Index 96h Bit 7-6 Name Reserved R/W Default Reserved. Description 51 Aug, 2010 V0.21P F71808E 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xC6-0xCE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that defined in 0xC6-0xCE. 10: Manual mode fan control, user can write expect RPM count 5-4 FAN3_MODE R/W 1h to 0xC2-0xC3, and F71808E will auto control duty cycle (PWM fan type) or voltage(linear fan type) to control fan speed. 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage(linear fan type) to 0xC3, and F71808E will output this value duty or voltage to control fan speed. 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xB6-0xBE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that defined in 0xB6-0xBE. 3-2 FAN2_MODE R/W 1h 10: Manual mode fan control, user can write expect RPM count to 0xB2-0xB3, and F71808E will auto control duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed. 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage (linear fan type) to 0xB3, and F71808E will output this value duty or voltage to control fan speed. 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xA6-0xAE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that defined in 0xA6-0xAE. 1-0 FAN1_MODE R/W 1h 10: Manual mode fan control, user can write expect RPM count to 0xA2-0xA3, and F71808E will auto control duty cycle (PWM fan type) or voltage(linear fan type) to control fan speed. 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage(linear fan type) to 0xA3, and F71808E will output this value duty or voltage to control fan speed. Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h Bit Name R/W Default Description 52 Aug, 2010 V0.21P F71808E 0000: Boundary hysteresis. (0~15 degree C) 7-4 FAN2_HYS R/W 4h Segment will change when the temperature over the boundary temperature and below the ( boundary - hysteresis ). 0000: Boundary hysteresis. (0~15 degree C) 3-0 FAN1_HYS R/W 4h Segment will change when the temperature over the boundary temperature and below the ( boundary - hysteresis ). Auto Fan3 Boundary Hystersis Select Register -- Index 99h Bit 7-4 Name Reserved R/W Default Reserved. 0000: Boundary hysteresis. (0~15 degree C) 3-0 FAN3_HYS R/W 2h Segment will change when the temperature over the boundary temperature and below the ( boundary - hysteresis ). Description Auto Fan Up Speed update Rate Select Register -- Index 9Bh (FAN_PROG_SEL = 0) Bit 7-6 5-4 Name Reserved SYSFAN2_ UP_RATE SYSFAN1_ UP_RATE CPUFAN _UP_RATE R/W Default R/W 1h Reserved. Fan3 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan2 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Description 3-2 R/W 1h 1-0 R/W 1h Auto Fan Down Speed update Rate Select Register -- Index 9Bh (FAN_RATE_PROG_SEL = 1) Bit 7 6 Name Reserved Direct_Update R/W Default R/W 0 1h Description Reserved. 0: Fan duty update rate is defined in bit[5:0] 1: Fan duty is updated to the desired Fan3 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan2 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz 53 Aug, 2010 V0.21P 5-4 FAN3_DOWN_RAT R/W E 3-2 FAN2_DOWN_RAT R/W E 1h 1-0 FAN1_DOWN_RAT R/W E 1h Fan1 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz F71808E FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE Index 9Ch Bit Name FAN2_STOP_DUT Y R/W Default Description When fan start, the FAN_CTRL2 will increase duty-cycle from 0 7-4 R/W 5h to this (value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 3-0 FAN1_STOP_DUT Y R/W 5h to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). FAN3 START UP DUTY-CYCLE/VOLTAGE Index 9Dh Bit 7-4 Name Reserved R/W Default Reserved. When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 3-0 FAN3_STOP_DUTY R/W 5h to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). Description FAN POWER-ON DEFAULT DUTY-CYCLE/VOLTAGE Index 9Eh Bit Name R/W Default 8'h66 Description Fan duty value immediately loaded after VDD is powered on. If 7-0 PWRON_DEF_DUTY R/W this byte is ever programmed, it will be used as the power-on default duty. Fan Fault Time Register -- Index 9Fh Bit 7 6-5 Name FAN_PROG_SEL Reserved R/W Default R/W 0 Reservd Description Set this bit to "1" will enable access registers of other bank. 54 Aug, 2010 V0.21P F71808E 0: The Fan duty value immediately loaded after VDD is powered-on is 100% if PWRON_DEF_DUTY is not been programmed. 4 FULL_DUTY_SEL R/W 1: The Fan duty value immediately loaded after VDD is powered-on is 40% if PWRON_DEF_DUTY is not been programmed. (pull up by internal 47K resistor). This register is power on trap by DTR#. 3-0 Reserved Reserved Fan1 Index A0h- AFh Address Attribute Default Value Description FAN1 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 count reading (LSB). RPM mode(CR96 bit0=0): FAN1 expect speed count value (MSB), in auto fan mode (CR96 A2h R/W 8'h00 bit1 0) this register is auto updated by hardware. A0h RO 8'h0f A1h RO 8'hff Duty mode(CR96 bit0=1): This byte is reserved byte. RPM mode(CR96 bit0=0): FAN1 expect speed count value (LSB) or expect PWM duty, in auto fan mode this register is auto updated by hardware and read only. A3h R/W 8'h01 Duty mode(CR96 bit0=1): The Value programming in this byte is duty value. In auto fan mode (CR96 bit1 Ex: 5 255 A4h A5h R/W R/W 8'h03 8'hff 0) this register is updated by hardware. 100% 5*100/255 % FAN1 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 full speed count reading (LSB). VT1 BOUNDARY 1 TEMPERATURE - Index A6h Bit Name R/W Default Description 55 Aug, 2010 V0.21P F71808E The 1 BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 expect value will load from segment 1 register (index AA)h. 7-0 BOUND1TMP1 R/W 3Ch When VT1 temperature is below this boundary - hysteresis, (60oC) FAN1 expect value will load from segment 2 register (index AAh). This byte is a 2's complement value ranging from -128'C ~ 127'C. st VT1 BOUNDARY 2 TEMPERATURE - Index A9 Bit Name R/W Default st Description The 2 BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 expect value will load from segment 2 register (index AB)h. 7-0 BOUND2TMP1 R/W 1Eh When VT1 temperature is below this boundary - hysteresis, (30oC) FAN1 expect value will load from segment 3 register (index ABh). This byte is a 2's complement value ranging from -128'C ~ 127'C. FAN1 SEGMENT 1 SPEED COUNT - Index AAh Bit Name R/W Default Description FFh The meaning of this register is depending on the (100%) FAN1_MODE(CR96) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: 7-0 SEC1SPEED1 R/W 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is (100-X)*32/X 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN1 SEGMENT 2 SPEED COUNT - Index ABh Bit Name R/W Default 56 Description Aug, 2010 V0.21P F71808E The meaning of this register is depending on the FAN1_MODE(CR96) 7-0 SEC2SPEED1 R/W D9h (85%) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN1 SEGMENT 3 SPEED COUNT Bit Name - Index AEh Description The meaning of this register is depending on the FAN1_MODE(CR96) R/W Default 7-0 SEC3SPEED1 R/W 80h 2'b00: The value that set in this byte is the relative expect fan (50%) speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN1 Temperature Mapping Select Bit 7 6 5 Name FAN1_TEMP_SEL_DI G Reserved FAN1_UP_T_EN FAN1_INTERPOLATIO N_EN R/W Default R/W R/W 0 0 0 - Index AFh Description This bit companying with FAN1_TEMP_SEL select the temperature source for controlling FAN1. Reserved Set 1 to force FAN1 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN1 duty movement when temperature over highest boundary. 0: The FAN1 duty will increases with the slope selected by 4 R/W 1 3 FAN1_JUMP_HIGH_E N R/W 1 FAN1_UP_RATE register. 1: The FAN1 duty will directly jumps to the value of SEC1SPEED1 register. This bit only activates in duty mode. 57 Aug, 2010 V0.21P F71808E This register controls the FAN1 duty movement when temperature under (highest boundary - hysteresis). 2 FAN1_JUMP_LOW_E N 0: The FAN1 duty will decreases with the slope selected by R/W 1 FAN1_DN_RATE register. 1: The FAN1 duty will directly jumps to the value of SEC2SPEED1 register. This bit only activates in duty mode. This registers companying with FAN1_TEMP_SEL_DIG select the temperature source for controlling FAN1. The following value is comprised by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL} 1-0 FAN1_TEMP_SEL R/W 1 000: fan1 follows PECI temperature (CR7Eh) 001: fan1 follows temperature 1 (CR72h). 010: fan1 follows temperature 2 (CR74h). 011: fan1 follows temperature 3 (CR76h). Otherwise: reserved. Fan2 Index B0h- BFh Address Attribute Default Value Description FAN2 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN2 count reading (LSB). RPM mode(CR96 bit2=0): FAN2 expect speed count value (MSB), in auto fan mode(CR96 B2h R/W 8'h00 bit3 0) this register is auto updated by hardware. B0h RO 8'h0f B1h RO 8'hff Duty mode(CR96 bit2=1): This byte is reserved byte. RPM mode(CR96 bit2=0): FAN2 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. B3h R/W 8'h01 Duty mode(CR96 bit2=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit3 Ex: 5 255 B4h R/W 8'h03 100% 0) this register is updated by hardware. 5*100/255 % FAN2 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating 58 Aug, 2010 V0.21P F71808E when reading. To read the fan count correctly, read MSB first and followed read the LSB. B5h R/W 8'hff FAN2 full speed count reading (LSB). VT2 BOUNDARY 1 TEMPERATURE - Index B6h Bit Name R/W Default st Description The 1 BOUNDARY temperature for VT2 in temperature mode. When VT2 temperature is exceed this boundary, FAN2 expect value will load from segment 1 register (index BA)h. 7-0 BOUND1TMP2 R/W 3Ch When VT2 temperature is below this boundary - hysteresis, (60oC) FAN2 expect value will load from segment 2 register (index BAh). This byte is a 2's complement value ranging from -128'C ~ 127'C. VT2 BOUNDARY 2 TEMPERATURE - Index B9 Bit Name R/W Default st Description The 2 BOUNDARY temperature for VT2 in temperature mode. When VT2 temperature is exceed this boundary, FAN2 expect 7-0 BOUND2TMP2 R/W 1Eh value will load from segment 2 register (index BB)h. (30oC) When VT2 temperature is below this boundary - hysteresis, FAN2 expect value will load from segment 3 register (index BBh). This byte is a 2's complement value ranging from -128'C ~ 127'C. FAN2 SEGMENT 1 SPEED COUNT - Index BAh Bit Name R/W Default Description 59 Aug, 2010 V0.21P F71808E The meaning of this register is depending on the FAN2_MODE(CR96) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: 7-0 SEC1SPEED2 R/W FFh (100%) 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is (100-X)*32/X 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN2 SEGMENT 2 SPEED COUNT - Index BBh Bit Name R/W Default FAN2_MODE(CR96) 7-0 SEC2SPEED2 R/W D9h (85%) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. Description The meaning of this register is depending on the FAN2 SEGMENT 3 SPEED COUNT Bit Name - Index BEh Description The meaning of this register is depending on the FAN2_MODE(CR96) R/W Default 7-0 SEC3SPEED2 R/W 80h (50%) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN2 Temperature Mapping Select - Index BFh Bit 7 6 Name FAN2_TEMP_SEL_DI G Reserved R/W Default R/W 0 This bit companying Description with FAN2_TEMP_SEL select the temperature source for controlling FAN2. Reserved 60 Aug, 2010 V0.21P F71808E 5 FAN2_UP_T_EN FAN2_INTERPOLATIO N_EN R/W 0 Set 1 to force FAN2 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN2 duty movement when temperature over highest boundary. 3 FAN2_JUMP_HIGH_E N 0: The FAN2 duty will increases with the slope selected by R/W 1 FAN2_UP_RATE register. 1: The FAN2 duty will directly jumps to the value of SEC1SPEED2 register. This bit only activates in duty mode. This register controls the FAN2 duty movement when temperature under (highest boundary - hysteresis). 2 FAN2_JUMP_LOW_E N 0: The FAN2 duty will decreases with the slope selected by R/W 1 FAN2_DN_RATE register. 1: The FAN2 duty will directly jumps to the value of SEC2SPEED2 register. This bit only activates in duty mode. This registers companying with FAN2_TEMP_SEL_DIG select the temperature source for controlling FAN2. The following value is comprised by {FAN2_TEMP_SEL_DIG, FAN2_TEMP_SEL} 1-0 FAN2_TEMP_SEL R/W 10 000: fan2 follows PECI temperature (CR7Eh) 001: fan2 follows temperature 1 (CR72h). 010: fan2 follows temperature 2 (CR74h). 011: fan2 follows temperature 3 (CR76h). Otherwise: reserved. 4 R/W 1 Fan3 Index C0h- CFh Address Attribute Default Value Description FAN3 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN3 count reading (LSB). RPM mode(CR96 bit4=0): C2h R/W 8'h00 FAN3 expect speed count value (MSB), in auto fan mode(CR96 bit5 0) this register is auto updated by hardware. C0h RO 8'h0F C1h RO 8'hff 61 Aug, 2010 V0.21P F71808E Duty mode(CR96 bit4=1): This byte is reserved byte. RPM mode(CR96 bit4=0): FAN3 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. C3h R/W 8'h01 Duty mode(CR96 bit4=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit5 Ex: 5 255 C4h C5h R/W R/W 8'h03 8'hff 100% 0) this register is updated by hardware. 5*100/255 % FAN3 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN3 full speed count reading (LSB). VT3 BOUNDARY 1 TEMPERATURE - Index C6h Bit Name R/W Default st Description 3Ch The 1 BOUNDARY temperature for VT3 in temperature mode. (60oC) When VT3 temperature is exceed this boundary, FAN3 expect value will load from segment 1 register (index CA)h. 7-0 BOUND1TMP3 R/W When VT3 temperature is below this boundary - hysteresis, FAN3 expect value will load from segment 2 register (index CAh). This byte is a 2's complement value ranging from -128'C ~ 127'C. VT3 BOUNDARY 2 TEMPERATURE - Index C9 Bit Name R/W Default st Description The 2 BOUNDARY temperature for VT3 in temperature mode. When VT3 temperature is exceed this boundary, FAN3 expect value will load from segment 2 register (index CB)h. 7-0 BOUND2TMP3 R/W 1Eh When VT3 temperature is below this boundary - hysteresis, (30oC) FAN3 expect value will load from segment 3 register (index CBh). This byte is a 2's complement value ranging from -128'C ~ 127'C. 62 Aug, 2010 V0.21P F71808E FAN3 SEGMENT 1 SPEED COUNT - Index CAh Bit Name R/W Default FAN3_MODE(CR96) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: 7-0 SEC1SPEED3 R/W FFh (100%) 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is (100-X)*32/X 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. Description The meaning of this register is depending on the FAN3 SEGMENT 2 SPEED COUNT - Index CBh Bit Name R/W Default FAN3_MODE(CR96) 7-0 SEC2SPEED3 R/W D9h (85%) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. Description The meaning of this register is depending on the FAN3 SEGMENT 3 SPEED COUNT - Index CEh Bit Name R/W Default FAN3_MODE(CR96) 7-0 SEC3SPEED3 R/W 80h (50%) 2'b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2'b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. Description The meaning of this register is depending on the FAN3 Temperature Mapping Select Bit 7 Name FAN3_TEMP_SEL_DI G - Index CFh Description This bit companying with FAN3_TEMP_SEL select the temperature source for controlling FAN3. 63 Aug, 2010 V0.21P R/W Default R/W 0 F71808E FAN3 PWM duty selection 6 PWM_FREQ_SEL R/W 0 0: 23.5KHz 1: 220Hz 5 FAN3_UP_T_EN FAN3_INTERPOLATIO N_EN R/W 0 Set 1 to force FAN3 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. 4 R/W 1 This register controls the FAN3 duty movement when temperature over highest boundary. 3 FAN3_JUMP_HIGH_E N 0: The FAN3 duty will increases with the slope selected by R/W 1 FAN3_UP_RATE register. 1: The FAN3 duty will directly jumps to the value of SEC1SPEED3 register. This bit only activates in duty mode. This register controls the FAN3 duty movement when temperature under (highest boundary - hysteresis). 2 FAN3_JUMP_LOW_E N 0: The FAN3 duty will decreases with the slope selected by R/W 1 FAN3_DN_RATE register. 1: The FAN3 duty will directly jumps to the value of SEC2SPEED3 register. This bit only activates in duty mode. This registers companying with FAN3_TEMP_SEL_DIG select the temperature source for controlling FAN3. The following value is comprised by {FAN3_TEMP_SEL_DIG, FAN3_TEMP_SEL} 1-0 FAN3_TEMP_SEL R/W 10 000: fan3 follows PECI temperature (CR7Eh) 001: fan3 follows temperature 1 (CR72h). 010: fan3 follows temperature 2 (CR74h). 011: fan3 follows temperature 3 (CR76h). Otherwise: reserved. 64 Aug, 2010 V0.21P F71808E 8.4 8.4.1 Bit KBC Registers (CR05) KBC Device Enable Register Index 30h Name R/W Default R/W 1 Reserved 0: disable KBC. 1: enable KBC. Description 7-1 Reserved 0 KBC_EN 8.4.2 Bit 7-0 Base Address High Register Index 60h Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of KBC command port address. The address of data port is command port address + 4; 8.4.3 Bit 7-0 Base Address Low Register Index 61h Name R/W Default 60h Description The LSB of KBC command port address. The address of data port is command port address + 4. BASE_ADDR_LO R/W 8.4.4 Bit 7-4 3-0 8.4.5 Bit 7-4 3-0 8.4.6 Bit KB IRQ Channel Select Register Index 70h Name Reserved SELKIRQ R/W Default R/W 1h Reserved. Select the IRQ channel for keyboard interrupt. Description Mouse IRQ Channel Select Register Index 72h Name Reserved SELMIRQ R/W Default R/W Ch Reserved. Select the IRQ channel for PS/2 mouse interrupt. Description Clock Select Register Index F0h Name R/W Default Description 00: select 6MHz clock as KBC clock input. 7-6 SELCLK_KBC R/W 10 01: select 8MHz clock as KBC clock input. 10: select 12MHz clock as KBC clock input (default). 11: select 16MHz clock as KBC clock input. 65 Aug, 2010 V0.21P F71808E 5-2 1 Reserved GA20_EN R/W 1 Reserved. 0: GATE20# software control. 1: GATE20# hardware speed up. 0: KBRST# software control. 1: KBRST# hardware speed up. 0 HKBRST R/W 1 8.4.7 Bit 7 6-5 Auto Swap Register Index FEh (Powered by VBAT) Name AUTO_DET_EN Reserved R/W Default R/W 1b Description 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. Reserved. 0: Keyboard/mouse not swap. 4 KB_MO_SWAP R/W 0b 1: Keyboard/mouse swap. This bit is set/clear by hardware if AUTO_DET_EN is set to "1". Users could also program this bit manually. 3-0 8.4.8 Bit 7-0 Reserved - - Reserved. User Wakeup Code Register Index FFh (Powered by VBAT) Name USER_WAKEUP_ CODE R/W Default R/W 29h Description This is user define wakeup code. Default is space. 8.5 8.5.1 Bit 7-4 3-0 8.5.2 Bit 7-5 4 GPIO Registers (CR06) GPIRQ Channel Select Register Index 70h Name Reserved SELGPIRQ R/W Default R/W 0h Reserved. Select the IRQ channel for GPIO interrupt. Description GPIO3 Output Enable Register Index C0h Name Reserved GPIO34_OE R/W Default R/W 0 Reserved. 0: GPIO34 is in input mode. 1: GPIO34 is in output mode. Description 66 Aug, 2010 V0.21P F71808E 3 2 1 0 GPIO33_OE GPIO32_OE GPIO31_OE GPIO30_OE R/W R/W R/W R/W 0 0 0 0 0: GPIO33 is in input mode. 1: GPIO33 is in output mode. 0: GPIO32 is in input mode. 1: GPIO32 is in output mode. 0: GPIO31 is in input mode. 1: GPIO31 is in output mode. 0: GPIO30 is in input mode. 1: GPIO30 is in output mode. 8.5.3 Bit 7-5 4 3 2 1 0 GPIO3 Output Data Register Index C1h Name Reserved GPIO34_VAL GPIO33_VAL GPIO32_VAL GPIO31_VAL GPIO30_VAL R/W Default R/W R/W R/W R/W R/W 1 1 1 1 1 Reserved. 0: GPIO34 outputs 0 when in output mode. 1: GPIO34 outputs 1 when in output mode. 0: GPIO33 outputs 0 when in output mode. 1: GPIO33 outputs 1 when in output mode. 0: GPIO32 outputs 0 when in output mode. 1: GPIO32 outputs 1 when in output mode. 0: GPIO31 outputs 0 when in output mode. 1: GPIO31 outputs 1 when in output mode. 0: GPIO30 outputs 0 when in output mode. 1: GPIO30 outputs 1 when in output mode. Description 8.5.4 Bit 7-5 4 3 2 1 8.5.5 Bit 7-5 4 GPIO3 Pin Status Register Index C2h Name Reserved GPIO34_IN GPIO33_IN GPIO32_IN GPIO31_IN R/W Default R R R R Reserved. The pin status of SYSFANOUT1/GPIO34. The pin status of PECI_REQ/ GPIO33. The pin status of PECI/ GPIO32. The pin status of VLDT_EN Description GPIO3 Drive Enable Register Index C3h Name Reserved R/W Default 0 Reserved 0: GPIO34 is open drain in output mode. 1: GPIO34 is push pull in output mode. 0: GPIO33 is open drain in output mode. 1: GPIO33 is push pull in output mode. 0: GPIO32 is open drain in output mode. 1: GPIO32 is push pull in output mode. Description GPIO34_DRV_EN R/W 3 GPIO33_DRV_EN R/W 0 2 GPIO32_DRV_EN R/W 0 67 Aug, 2010 V0.21P F71808E 1 GPIO31_DRV_EN R/W 0 0: GPIO31 is open drain in output mode. 1: GPIO31 is push pull in output mode. 0: GPIO30 is open drain in output mode. 1: GPIO30 is push pull in output mode. 0 GPIO30_DRV_EN R/W 0 8.5.6 Bit 7 6 5 4 3 2 1 0 GPIO2 Output Enable Register Index D0h Name GPIO27_OE GPIO26_OE GPIO25_OE GPIO24_OE GPIO23_OE GPIO22_OE GPIO21_OE GPIO20_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO27 is in input mode. 1: GPIO27 is in output mode. 0: GPIO26 is in input mode. 1: GPIO26 is in output mode. 0: GPIO25 is in input mode. 1: GPIO25 is in output mode. 0: GPIO24 is in input mode. 1: GPIO24 is in output mode. 0: GPIO23 is in input mode. 1: GPIO23 is in output mode. 0: GPIO22 is in input mode. 1: GPIO22 is in output mode. 0: GPIO21 is in input mode. 1: GPIO21 is in output mode. 0: GPIO20 is in input mode. 1: GPIO20 is in output mode. 8.5.7 Bit 7 6 5 4 3 2 1 0 GPIO2 Output Data Register Index D1h Name GPIO27_VAL GPIO26_VAL GPIO25_VAL GPIO24_VAL GPIO23_VAL GPIO22_VAL GPIO21_VAL GPIO20_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO27 outputs 0 when in output mode. 1: GPIO27 outputs 1 when in output mode. 0: GPIO26 outputs 0 when in output mode. 1: GPIO26 outputs 1 when in output mode. 0: GPIO25 outputs 0 when in output mode. 1: GPIO25 outputs 1 when in output mode. 0: GPIO24 outputs 0 when in output mode. 1: GPIO24 outputs 1 when in output mode. 0: GPIO23 outputs 0 when in output mode. 1: GPIO23 outputs 1 when in output mode. 0: GPIO22 outputs 0 when in output mode. 1: GPIO22 outputs 1 when in output mode. 0: GPIO21 outputs 0 when in output mode. 1: GPIO21 outputs 1 when in output mode. 0: GPIO20 outputs 0 when in output mode. 1: GPIO20 outputs 1 when in output mode. 68 Aug, 2010 V0.21P F71808E 8.5.8 Bit 7 6 5 4 3 2 1 0 8.5.9 Bit 7 6 5 4 3 2 1 0 GPIO2 Pin Status Register Index D2h Name GPIO27_IN GPIO26_IN GPIO25_IN GPIO24_IN GPIO23_IN GPIO22_IN GPIO21_IN GPIO20_IN R/W Default R R R R R R R R Description The pin status of PSIN#/GPIO27. The pin status of RESETCON#/GPIO26. The pin status of GPIO25/LEDVCC. The pin status of GPIO24/LEDVSB. The pin status of GPIO23/WDTRST#/SYSFANIN2. The pin status of GPIO22/SYSFANOUT2. The pin status of GPIO21/OVT#/SYSFANIN2. The pin status of GPIO20/PME#. GPIO2 Drive Enable Register Index D3h Name R/W Default 0 0 0 0 0 0 0 0 Description 0: GPIO27 is open drain in output mode. 1: GPIO27 is push pull in output mode. 0: GPIO26 is open drain in output mode. 1: GPIO26 is push pull in output mode. 0: GPIO25 is open drain in output mode. 1: GPIO25 is push pull in output mode. 0: GPIO24 is open drain in output mode. 1: GPIO24 is push pull in output mode. 0: GPIO23 is open drain in output mode. 1: GPIO23 is push pull in output mode. 0: GPIO22 is open drain in output mode. 1: GPIO22 is push pull in output mode. 0: GPIO21 is open drain in output mode. 1: GPIO21 is push pull in output mode. 0: GPIO20 is open drain in output mode. 1: GPIO20 is push pull in output mode. GPIO27_DRV_EN R/W GPIO26_DRV_EN R/W GPIO25_DRV_EN R/W GPIO24_DRV_EN R/W GPIO23_DRV_EN R/W GPIO22_DRV_EN R/W GPIO21_DRV_EN R/W GPIO20_DRV_EN R/W 8.5.10 Bit 7-6 5 4 3 2 1-0 GPIO2 PME Enable Register Index D4h Name Reserved R/W Default 0 0 0 0 Reserved. When GPIO25_PME_STS is 1 and GPIO25_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO24_PME_STS is 1 and GPIO24_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO23_PME_STS is 1 and GPIO23_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO22_PME_STS is 1 and GPIO22_PME_EN is set to 1, a GPIO PME event will be generated. Reserved. Description GPIO25_PME_EN R/W GPIO24_PME_EN R/W GPIO23_PME_EN R/W GPIO22_PME_EN R/W Reserved - 69 Aug, 2010 V0.21P F71808E 8.5.11 Bit 7-6 GPIO2 Input Detection Select Register Index D5h Name Reserved R/W Default Reserved. When GPIO25 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO24 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO23 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO22 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge Reserved. Description 5 GPIO25_DET_SEL R/W 0 4 GPIO24_DET_SEL R/W 0 3 GPIO23_DET_SEL R/W 0 2 GPIO22_DET_SEL R/W 0 1-0 8.5.12 Bit 7-6 5 4 3 2 1-0 8.5.13 Bit Reserved - - GPIO2 Event Status Register Index D6h Name Reserved R/W Default 0 0 0 0 Reserved. When GPIO25 is in input mode and a GPIO25 input is detected, this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO24 is in input mode and a GPIO24 input is detected, this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO23 is in input mode and a GPIO23 input is detected, this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO22 is in input mode and a GPIO22 input is detected, this bit will be set to 1. Write a 1 to this bit will clear it to 0. Reserved. Description GPIO25_PME_ST R/W S C GPIO24_PME_ST R/W S C GPIO23_PME_ST R/W S C GPIO22_PME_ST R/W S C Reserved - GPIO2 Output Mode Status Register Index D7h Name R/W Default Description GPIO25_MODE is used to select the output mode of GPIO25: 00: High Level Mode 01: Inverted Level Mode 10: High Pulse Mode 11: Low Pulse Mode 7-6 GPIO25_MODE R/W 0 70 Aug, 2010 V0.21P F71808E 5-4 GPIO24_MODE R/W 0 GPIO24_MODE is used to select the output mode of GPIO24: 00: Level Mode 01: Inverted Level Mode 10: High Pulse Mode 11: Low Pulse Mode GPIO23_MODE is used to select the output mode of GPIO23: 00: Level Mode 01: Inverted Level Mode 10: High Pulse Mode 11: Low Pulse Mode GPIO22_MODE is used to select the output mode of GPIO22: 00: Level Mode 01: Inverted Level Mode 10: High Pulse Mode 11: Low Pulse Mode 3-2 GPIO23_MODE R/W 0 1-0 GPIO22_MODE R/W 0 8.5.14 Bit GPIO2 Pulse Width of Pulse Mode Status Register Index D8h Name R/W Default Description GPIO25_PW_SEL is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms GPIO24_PW_SEL is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms GPIO23_PW_SEL is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms GPIO22_PW_SEL is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms 7-6 GPIO25_PW_SEL R/W 0 5-4 GPIO24_PW_SEL R/W 0 3-2 GPIO23_PW_SEL R/W 0 1-0 GPIO22_PW_SEL R/W 0 8.5.15 Bit 7-5 4 GPIO1 Output Enable Register Index E0h Name Reserved GPIO14_OE R/W Default R/W 0 Reserved. 0: GPIO14 is in input mode. 1: GPIO14 is in output mode. 71 Aug, 2010 V0.21P Description F71808E 3 2 1 0 GPIO13_OE GPIO12_OE GPIO11_OE GPIO10_OE R/W R/W R/W R/W 0 0 0 0 0: GPIO13 is in input mode. 1: GPIO13 is in output mode. 0: GPIO12 is in input mode. 1: GPIO12 is in output mode. 0: GPIO11 is in input mode. 1: GPIO11 is in output mode. 0: GPIO10 is in input mode. 1: GPIO10 is in output mode. 8.5.16 Bit 7-5 4 3 2 1 0 GPIO1 Output Data Register Index E1h Name Reserved GPIO14_VAL GPIO13_VAL GPIO12_VAL GPIO11_VAL GPIO10_VAL R/W Default R/W R/W R/W R/W R/W 1 1 1 1 1 Reserved. 0: GPIO14 outputs 0 when in output mode. 1: GPIO14 outputs 1 when in output mode. 0: GPIO13 outputs 0 when in output mode. 1: GPIO13 outputs 1 when in output mode. 0: GPIO12 outputs 0 when in output mode. 1: GPIO12 outputs 1 when in output mode. 0: GPIO11 outputs 0 when in output mode. 1: GPIO11 outputs 1 when in output mode. 0: GPIO10 outputs 0 when in output mode. 1: GPIO10 outputs 1 when in output mode. Description 8.5.17 Bit 7-5 4 3 2 1 0 8.5.18 Bit 7-5 4 3 2 1 GPIO1 Pin Status Register Index E2h Name Reserved GPIO14_IN GPIO13_IN GPIO12_IN GPIO11_IN GPIO10_IN R/W Default R R R R R Reserved. The pin status of PSOUT#/GPIO14. The pin status of MCLK/GPIO13. The pin status of MDAT/GPIO12. The pin status of KCLK/GPIO11. The pin status of KDAT/GPIO10. Description GPIO1 Drive Enable Register Index E3h Name Reserved R/W Default 0 0 0 0 Reserved. 0: GPIO14 is open drain in output mode. 1: GPIO14 is push pull in output mode. 0: GPIO13 is open drain in output mode. 1: GPIO13 is push pull in output mode. 0: GPIO12 is open drain in output mode. 1: GPIO12 is push pull in output mode. 0: GPIO11 is open drain in output mode. 1: GPIO11 is push pull in output mode. Description GPIO14_DRV_EN R/W GPIO13_DRV_EN R/W GPIO12_DRV_EN R/W GPIO11_DRV_EN R/W 72 Aug, 2010 V0.21P F71808E 0 GPIO10_DRV_EN R/W 0 0: GPIO10 is open drain in output mode. 1: GPIO10 is push pull in output mode. 8.5.19 Bit 7 6 5 4 3 2 1 0 GPIO0 Output Enable Register Index F0h Name GPIO07_OE GPIO06_OE GPIO05_OE GPIO04_OE GPIO03_OE GPIO02_OE GPIO01_OE GPIO00_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO07 is in input mode. 1: GPIO07 is in output mode. 0: GPIO06 is in input mode. 1: GPIO06 is in output mode. 0: GPIO05 is in input mode. 1: GPIO05 is in output mode. 0: GPIO04 is in input mode. 1: GPIO04 is in output mode. 0: GPIO03 is in input mode. 1: GPIO03 is in output mode. 0: GPIO02 is in input mode. 1: GPIO02 is in output mode. 0: GPIO01 is in input mode. 1: GPIO01 is in output mode. 0: GPIO00 is in input mode. 1: GPIO00 is in output mode. 8.5.20 Bit 7 6 5 4 3 2 1 0 GPIO0 Output Data Register Index F1h Name GPIO07_VAL GPIO06_VAL GPIO05_VAL GPIO04_VAL GPIO03_VAL GPIO02_VAL GPIO01_VAL GPIO00_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO07 outputs 0 when in output mode. 1: GPIO07 outputs 1 when in output mode. 0: GPIO06 outputs 0 when in output mode. 1: GPIO06 outputs 1 when in output mode. 0: GPIO05 outputs 0 when in output mode. 1: GPIO05 outputs 1 when in output mode. 0: GPIO04 outputs 0 when in output mode. 1: GPIO04 outputs 1 when in output mode. 0: GPIO03 outputs 0 when in output mode. 1: GPIO03 outputs 1 when in output mode. 0: GPIO02 outputs 0 when in output mode. 1: GPIO02 outputs 1 when in output mode. 0: GPIO01 outputs 0 when in output mode. 1: GPIO01 outputs 1 when in output mode. 0: GPIO00 outputs 0 when in output mode. 1: GPIO00 outputs 1 when in output mode. 8.5.21 Bit 7 6 GPIO Pin Status Register Index F2h Name GPIO07_IN GPIO06_IN R/W Default R R Description The pin status of SIN/GPIO07. The pin status of SOUT/GPIO06/2E_4E. 73 Aug, 2010 V0.21P F71808E 5 4 3 2 1 0 8.5.22 Bit 7 6 5 4 3 2 1 0 GPIO05_IN GPIO04_IN GPIO03_IN GPIO02_IN GPIO01_IN GPIO00_IN R R R R R R The pin status of DSR#/GPIO05. The pin status of RTS#/GPIO04. The pin status of DTR#/GPIO03/40_100. The pin status of CTS#/GPIO02. The pin status of RI#/GPIO01. The pin status of DCD#/GPIO00. GPIO Drive Enable Register Index F3h Name R/W Default 0 0 0 0 0 0 0 0 Description 0: GPIO07 is open drain in output mode. 1: GPIO07 is push pull in output mode. 0: GPIO06 is open drain in output mode. 1: GPIO06 is push pull in output mode. 0: GPIO05 is open drain in output mode. 1: GPIO05 is push pull in output mode. 0: GPIO04 is open drain in output mode. 1: GPIO04 is push pull in output mode. 0: GPIO03 is open drain in output mode. 1: GPIO03 is push pull in output mode. 0: GPIO02 is open drain in output mode. 1: GPIO02 is push pull in output mode. 0: GPIO01 is open drain in output mode. 1: GPIO01 is push pull in output mode. 0: GPIO00 is open drain in output mode. 1: GPIO00 is push pull in output mode. GPIO07_DRV_EN R/W GPIO06_DRV_EN R/W GPIO05_DRV_EN R/W GPIO04_DRV_EN R/W GPIO03_DRV_EN R/W GPIO02_DRV_EN R/W GPIO01_DRV_EN R/W GPIO00_DRV_EN R/W 8.6 WDT Registers (CR07) Configuration Registers 8.6.1 Bit 7-1 0 WDT Enable Register Index 30h Name Reserved WDT_EN R/W Default R/W 0 0 Reserved 0: disable watch dog timer 1: enable watch dog timer Description 8.6.2 Bit 7-0 8.6.3 Bit 7-0 Base Address High Register Index 60h Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of VID base address. Base Address Low Register Index 61h Name R/W Default 00h Description The LSB of VID base address. 74 Aug, 2010 V0.21P BASE_ADDR_LO R/W F71808E Device Registers 8.6.4 Bit 7 6-4 3-0 8.6.5 Bit 7-0 8.6.6 Bit 7 6 5 4 Configuration Register Index F0h (offset + 00h) Name WDOUT_EN Reserved Reserved R/W Default R/W 0 Description If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output is enabled. Reserved Reserved Register Index F2h~F4h Name Reserved R/W Default Reserved Description Watchdog Timer Configuration Register 1 Index 05h Name Reserved R/W Default 0 0 0 Reserved If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit will clear it to 0. If this bit is set to 1, the counting of watchdog time is enabled. Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit. Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. Select output polarity of RSTOUT# (1: high active, 0: low active) by setting this bit. Select output pulse width of RSTOUT# Description WDTMOUT_STS R/W WD_EN WD_PULSE R/W R/W 3 WD_UNIT R/W 0 2 WD_HACTIVE R/W 0 1:0 WD_PSWIDTH R/W 0 0: 1 ms 2: 125 ms 1: 25 ms 3: 5 sec 8.6.7 Bit 7:0 8.6.8 Bit 7 6 Watchdog Timer Configuration Register 2 Index 06h Name WD_TIME R/W Default R/W 0 Time of watchdog timer Description WDT PME Register Index 07h Name WDT_PME WDT_PME_EN R/W Default R R/W 0 0 0: Disable WDT PME. 1: Enable WDT PME. Description WDT PME real time status. 75 Aug, 2010 V0.21P F71808E 0: No WDT PME occurred. 5 WDT_PME_ST R/W 0 1: WDT PME occurred. The WDT PME is occurred one unit before WDT timeout. 4-0 Reserved Reserved 8.7 PME, ACPI, Power Saving Registers (CR0A) Configuration Register 8.7.1 Bit 7-1 0 Device Enable Register Index 30h Name Reserved PME_EN R/W Default R/W 0 Reserved 0: disable PME. 1: enable PME. Description 8.7.2 Bit 7 6 5 EuP Enable Register Index E0h Name EuP_EN Reserved EVENT_EN R/W Default R/W R/W 0 0 0 0 : disable EuP function 1: enable EuP function Reserved. Event input enable. 0: disable EVENT_IN# function. 1: Function of pin 19 is EVENT_IN# VSB_CTRL_1 enable. 0: disable VSB_CTRL_1 function. 1: Function of pin 20 is VSB_CTRL_1 Reserved EVENT_IN# PME event enable. 0: disable EVENT_IN# PME event. 1: enable EVENT_IN# PME event EVENT_IN# PSOUT event enable. 0: disable EVENT_IN# PSOUT event. 1: enable EVENT_IN# PSOUT event Description 4 3-2 1 VSB_CTRL_1_EN Reserved EVENT_PME_EN R/W R/W 0 0 0 EVENT_PSOUT_EN R/W 0 8.7.3 Bit EuP control register Index E1h Name R/W Default Description Write these two bits to select Boot Mode for Always Off/ Always On/ Keep Last State. 00:Default Always Off 11:Support Always On and Keep Last State 10:Reserved 01:Reserved Reserved 7-6 Boot_Mode R/W 11 5-4 Reserved - - 76 Aug, 2010 V0.21P F71808E 3 2 1 0 S5 _CTRL_1_DIS S5 _CTRL_0_DIS AC_ CTRL_1_DIS AC_ CTRL_0_DIS R/W R/W R/W R/W 1 1 0 0 If clear to "0" CTRL_1 will output Low when S5 state. Else If set to "1" CTRL_1 will output High when S5 state. If clear to "0" CTRL_0 will output Low when S5 state. Else If set to "1" CTRL_0 will output High when S5 state. If clear to "0" CTRL_1 will output Low when after AC lost. Else If set to "1" CTRL_1 will output High when after AC lost. If clear to "0" CTRL_0 will output Low when after AC lost. Else If set to "1" CTRL_0 will output High when after AC lost. 8.7.4 Bit 7 6 5 4 EuP control register Index E2h Name AC_LOST Reserved VSB_CTRL_EN[1] VSB_CTRL_EN[0] R/W Default R/WC R/W R/W R/W 0 1'b0 1'b0 Reserved 0: disable eup_ctrl2 assert rsmrst low 1: enable eup_ctrl2 assert rsmrst low 0: disable eup_ctrl1 assert rsmrst low 1: enable eup_ctrl1 assert rsmrst low Device into S5 state will check S5# signal and VCC_IN pin status, but when user clear this bit to 0. Device into S5 state will not check S5# become low. Device into S5 state will check S5# signal and VCC_IN pin status, but when user clear this bit to 0. Device into S5 state will not check VCC_IN become low. Device detects VSB5V power ok (4.4V) and VSB3V_IN become high, and after 60ms de-bounce time RSMRST will become high. But when user set this bit to 1. RSMRST will not check VSB5V power ok. Reserved. Description Set 1 if AC lost, and write 1 to clear. 3 S5_DET_S5# R/W 1 2 S5_DET_VCC R/W 1 1 0 RSMRST_DET_5V_N R/W - 0 - Reserved 8.7.5 Bit .7-0 EuP PSIN deb-register Index E3h Name PS_DEB_TIME R/W Default R/W 0x13 Description PS_IN pin input de-bounce time default is 20mSec 8.7.6 Bit 7-0 EuP RSMRST deb-register Index E4h Name R/W Default 0x09 Description RSMRST internal de-bounce time default is 10mSec RSMRST_DEB_TIM R/W E 8.7.7 Bit 7-0 EuP PSOUT deb-register Index E5h Name R/W Default Description PS_OUT_PULSE_W R/W 0xC7 PS_OUT_OUT output Pulse width default is 200mSec low pulse 77 Aug, 2010 V0.21P F71808E 8.7.8 Bit 7-0 EuP PSON deb-register Index E6h Name PS_ON_DEB_TIME R/W Default R/W 0x09 Description PSON_IN pin input de-bounce time default is 10mSec 8.7.9 Bit 7-0 EuP S5 deb-register Index E7h Name S5_DEB_TIME R/W Default R/W 0x63 Description S5# pin input de-bounce time The unit of this byte is 64ms. Default is 6.4Sec 8.7.10 Bit 7-6 5 4 3 2 1 0 EuP Wakeup Event Enable Register Index E8h Name Reserved Reserved GP_WAKEUP_EN R/W Default R/W 1 0 0 0 0 Reserved. Reserved. Enable EVENT_IN# event to wakeup. Enable GPIO PME event to wakeup. Enable EuP Watchdog Timer timeout event to wakeup. See index EDh and EEh. Enable Mouse PME event to wakeup. Enable Keyboard PME event to wakeup. Description EVENT_WAKEUP_EN R/W TMOUT_WAKEUP_EN R/W MO_WAKEUP_EN KB_WAKEUP_EN R/W R/W 8.7.11 Bit 7-4 4 3-2 1 0 EuP Watchdog Control Register Index EDh Name Revered WD_TMOUT Revered WD_UNIT WD_EN R/W Default R/WC R/W R/W 0 0 0 Reserved. EuP watchdog timer timeout status. Write 1 to clear. Reserved. 0: unit of WD_TIME is 1 sec. 1: unit of WD_TIME is 1 minute. Enable EuP watchdog timer. Description 8.7.12 Bit 7-0 EuP Watchdog Time Register Index EEh Name WD_TIME R/W Default R/W 0 Description EuP watchdog timer count time register. Start to count down when WD_EN is set. When reaching 0, WD_EN will auto clear and WD_TMOUT is set. A wakeup event will assert if enabled. 8.7.13 Bit 7 PME Event Enable Register 1 Index F0h Name WDT_PME_EN R/W Default R/W 0 Description WDT PME event enable. 0: disable WDT PME event. 1: enable WDT PME event. Mouse PME event enable. 0: disable mouse PME event. 1: enable mouse PME event. 6 MO_PME_EN R/W 0 78 Aug, 2010 V0.21P F71808E 5 KB_PME_EN R/W 0 Keyboard PME event enable. 0: disable keyboard PME event. 1: enable keyboard PME event. Hardware monitor PME event enable. 0: disable hardware monitor PME event. 1: enable hardware monitor PME event. Reserved UART PME event enable. 0: disable UART PME event. 1: enable UART PME event. Reserved 4 3-2 1 0 8.7.14 Bit 7 HM_PME_EN Reserved UR_PME_EN Reserved R/W R/W - 0 0 - PME Event Enable Register 2 Index F1h Name WDT_PME_ST R/W Default R/W C Description WDT PME event status. 0: WDT has no PME event. 1: WDT has a PME event to assert. Write 1 to clear to be ready for next PME event. Mouse PME event status. 0: Mouse has no PME event. 1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME event. Keyboard PME event status. 0: Keyboard has no PME event. 1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next PME event. Hardware monitor PME event status. 0: Hardware monitor has no PME event. 1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. Reserved UART PME event status. 0: UART has no PME event. 1: UART has a PME event to assert. Write 1 to clear to be ready for next PME event. Reserved 6 MO_PME_ST R/W C - 5 KB_PME_ST R/W C - 4 3-2 1 0 8.7.15 HM_PME_ST Reserved UR_PME_ST Reserved R/W C R/W - - PME Event Status Register Index F2h Bit 7-2 1 0 Name Reserved Reserved GP_PME_EN R/W Default R/W 0 Reserved Reserved. Description GPIO PME event enable. 0: disable GPIO PME event. 1: enable GPIO PME event. 79 Aug, 2010 V0.21P F71808E 8.7.16 Bit 7-4 3 2 1 0 PME Event Status Register Index F3h Name Reserved EUP_PME_ST Reserved Reserved R/W Default R/W - Description Reserved EUP PME event status. 0: EUP has no PME event. 1: EUP has a PME event to assert. Write 1 to clear to be ready for next PME event. Reserved Reserved. GPIO PME event status. 0: GPIO has no PME event. 1: GPIO has a PME event to assert. Write 1 to clear to be ready for next PME event. - GP_PME_ST R/W - 8.7.17 Bit 7 6-5 4 3 Keep Last State Select Register Index F4h Name Reserved Reserved EN_KBWAKEUP R/W Default R/W R/W R/W 0 0 0 0 Reserved Reserved Set one to enable keyboard wakeup event asserted via PWSOUT#. Set one to enable mouse wakeup event asserted via PWSOUT#. The ACPI Control the PSON_N to always on or always off or keep last state 00 : Keep last state 10 : Always on 01 : Bypass mode. 11: Always off When VSB 3V comes, it will set to 1, and write 1 to clear it Description EN_MOWAKEUP R/W 2-1 PWRCTRL R/W 11 0 8.7.18 Bit VSB_PWR_LOSS R/W 0 VDDOK Delay Register Index F5h Name R/W Default Description The additional PWROK delay. 00: no delay 01: 100ms. 10: 200ms 11: 400ms. 0: RESETCON# will assert via PWROK. 1: RESETCON# will assert via RESETOUT1# and RESETOUT2#. The PWROK delay timing from VDD3VOK by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms Reserved. 7-6 PWROK_DELAY R/W 0 5 RSTCON_EN R/W 1 4-3 VDD_DELAY R/W 11 2-0 Reserved - - 80 Aug, 2010 V0.21P F71808E 8.7.19 Bit 7 PCIRST Control Register Index F6h Name S3_SEL R/W Default R/W 0 Description Select the KBC S3 state. 0: Enter S3 state when internal VDD3VOK signal de-asserted. 1: Enter S3 state when S3# is low or the TS3 register is set to 1. 0: PSON# is the inverted of S3# signal. 1: PSON# will sink low only if the time after the last turn-off elapse at least 4 seconds. Reserved. Write "0" to this bit will force RESETOUT2# to sink low. Write "0" to this bit will force RESETOUT1# to sink low. 6 5-2 1 0 PSON_DEL_EN Reserved R/W - 0 1 1 RESETOUT2_GAT R/W E RESETOUT1_GAT R/W E 8.7.20 Bit 7-4 3 2 1 0 8.7.21 Bit 7-6 Power Sequence Control Register Index F7h Name Reserved R/W Default R/W 0 0 0 0 Dummy register. 0: Disable WDT assert to PWROK pin. 1: Enable WDT assert to PWROK pin. Write "1" to generate a 250ms low pulse from PWROK pin. 0: 3VSBSW# sinks low in S5 state. 1: 3VSBSW# is tri-state in S5 state. Reserved. Description WDT_PWROK_EN R/W PWROK_250MS VSB_GATE_TRI Reserved W R/W - LED VCC Mode Select Register Index F8h Name Reserved R/W Default Reserved Select LED_VCC mode in S5 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VCC mode in S3 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VCC mode in S0 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Description 5-4 LED_VCC_S5_MO R/W DE 0 3-2 LED_VCC_S3_MO R/W DE 0 1-0 LED_VCC_S0_MO R/W DE 0 8.7.22 Bit LED VSB Mode Select Register Index F9h Name R/W Default Description 81 Aug, 2010 V0.21P F71808E 7-6 Reserved Reserved Select LED_VSB mode in S5 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VSB mode in S3 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VSB mode in S0 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. 5-4 LED_VSB_S5_MO R/W DE 0 3-2 LED_VSB_S3_MO R/W DE 0 1-0 LED_VSB_S0_MO R/W DE 0 8.7.23 Bit 7-2 RI De-bounce Select Register Index FEh Name Reserved R/W Default Reserved Select RI de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms. Description 1-0 RI_DB_SEL R/W 0 82 Aug, 2010 V0.21P F71808E 9. Electrical Characteristics 9.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to 150 UNIT V V C C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 9.2 DC Characteristics (Ta = 0 C to 70 C, VDD = 3.3V 10%, VSS = 0V) (Note) PARAMETER Temperature Error, Remote Diode Supply Voltage range Average operating supply current Standby supply current Resolution Power on reset threshold Diode source current CONDITONS 60 oC < TD < 145 oC, VCC = 3.0V to 3.6V 0 oC | MIN 3.0 TYP 1 1 3.3 8 5 1 2.2 95 10 MAX 3 3 3.6 Unit o C V mA uA o C V uA uA 2.4 High Level Low Level PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD12ts5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink capability, 5V tolerance. Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Output Low Current IOL +12 mA VOL = 0.4V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0V I/OD16t5v-TTL level bi-directional pin, Open-drain output with16 mA sink capability, 5V tolerance. Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Output Low Current IOL +16 mA VOL = 0.4V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0V I/OOD12t-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can programming to open-drain function. 83 Aug, 2010 V0.21P Input Low Threshold Voltage Vt0.8 V VDD = 3.3 V Input High Threshold Voltage Vt+ 2.0 V VDD = 3.3 V Output Low Current IOL -12 -9 mA VOL = 0.4 V Output High Current IOH +9 +12 mA VOH = 2.4V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0V I/O12t- TTL level bi-directional pin, Output pin with 12mA source-sink capability. Input Low Threshold Voltage Vt0.6 V VDD = 3.3 V Input High Threshold Voltage Vt+ 0.9 V VDD = 3.3 V Output High Current IOH +9 +12 mA VOH = 2.4V Input High Leakage ILIH +1 A VIN = 1.2V Input Low Leakage ILIL -1 A VIN = 0V INts - TTL level input pin with schmitt trigger Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0 V INt5v - TTL level input pin with 5V tolerance. Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0 V INts5v - TTL level input pin with schmitt trigger, 5V tolerance. Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Input High Leakage ILIH +1 A VIN = VDD Input Low Leakage ILIL -1 A VIN = 0 V OD12-Open-drain output with12 mA sink capability. Output Low Current IOL -12 mA VOL = 0.4V OD12-5v-Open-drain output with12 mA sink capability, 5V tolerance. Output Low Current IOL -12 mA VOL = 0.4V OD24-Open-drain output with 24 mA sink capability. Output Low Current IOL -24 mA VOL = 0.4V OD16-u10-5v-Open-drain output with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. Output Low Current IOL -16 mA VOL = 0.4V O8- Output pin with 8 mA source-sink capability. Output High Current IOH +6 +8 mA VOH = 2.4V O8-u47-5v- Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. Output High Current IOH +6 +8 mA VOH = 2.4V O12- Output pin with 12 mA source-sink capability. Output High Current IOH +9 +12 mA VOH = 2.4V O30- Output pin with 30 mA source-sink capability. F71808E 84 Aug, 2010 V0.21P F71808E 10.Ordering Information Part Number F71808EU Package Type 64-TQFP Green Package Production Flow Commercial, 0C to +70C Fintek F71808EU XXXXLAB XXXXXX.X Version Identification: Ex: For LAB version The version shows on RED area. Ex: LAB 85 Aug, 2010 V0.21P F71808E 11.Package Dimensions 64 TQFP Feature Integration Technology Inc. Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 86 Aug, 2010 V0.21P F71808E 12.Application Circuit VSB5V (from ATX) R1 10 C1 0.1u C2 0.1u R2 4.7k D2+ D1+ VREF VIN5 VIN4 VDIMM(VIN3) VLDT(VIN2) VCORE(VIN1) VSB3V D1 1N5819 RSMRST# 2 ATX_PWR_GD PWOK PWOK R3 4.7k VBAT VSB3V VCC3V 1 RSMRST# PSON# S3# RSMRST# and PWROK pull-up C3 0.1u U1 VSB3V DTR1# SOUT1 C4 0.1u 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSB CPUVCORE(VIN1) VLDT/VIN2 VDIMM/VIN3 VIN4 VIN5 VREF D1+ D2+ AGND(D-) 5VSB_IN VBAT RSMRST# PWROK PSON# SLP_S3# R4 1K R5 1K VCORE_EN VLDT_EN PECI PECI_REQ DCD1# RI1# CTS1# DTR1# RTS1# DSR1# SOUT1 SIN1 FANIN1 FANCTL1 FANIN2 FANCTL2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VCORE_EN/GPIO30 VLDT_EN/GPIO31 PECI/GPIO32 PECI_REQ/GPIO33 DCD#/GPIO00 RI#/GPIO01 CTS#/GPIO02 DTR#/GPIO03/40_100 RTS#/GPIO04 DSR#/GPIO05 SOUT/GPIO06/2E_4E SIN/GPIO07 CPUFANIN CPUFANOUT SY SFANIN1 SY SFANOUT1/GPIO34 PSOUT#/GPIO14 PSIN#/GPIO27 SLP_S5# RESETOUT2# RESETOUT1# RESETCON#/GPIO26 CTRL0# F71808E VSB 3VSBSW# GPIO25/LEDVCC GPIO24/LEDVSB GPIO23/WDTRST#/SY SFANIN2 GPIO22/SY SFANOUT2/CTRL1# GPIO21/OVT#/SY SFANIN2/EVENT_IN# GPIO20/PME# MCLK/GPIO13 VCC LRESET# SERIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 PCICLK CLKIN GND KBRST# GA20 KDAT/GPIO10 KCLK/GPIO11 MDAT/GPIO12 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PWSOUT# PWSIN# S5# PCIRST2# PCIRST1# RESETIN# CTRL0# 3VSBSW# LED_VCC LED_VSB FANIN3 CTRL1# EVENT_IN# PME# MCLK VSB5V (from ATX) C5 100uF R6 4.7K CTRL1# R7 1k C6 1uF Q1 MOSFET P wake up VSB (for Device) POWER-ON TRIP PIN NO. 59(SOUT1) 56(DTR1#) Symbol Config4E_2E FAN40_100 Value 1 0 1 0 Description Configuration Register I/O port is 4E/4F.(Default) Configuration Register I/O port is 2E/2F. FAN power on speed is the last programmed value. FAN power on speed is 100%. VCC3V C7 100uF VSB5V (from ATX) C8 100uF R9 4.7K MDAT KCLK KDAT GA20 KBRST# CTRL0# R10 1k C10 1uF VSB5V (from ATX) R11 4.7K EVENT_IN# wake up ev ent Q2 MOSFET P 5VSB (for Device) 3VSBSW# R8 10k C9F71808E 0.1u LRESET# SERIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 PCICLK CLK_24/48M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3VSBSW# Pull-down C11 100uF F71808E Title <F71808E> Feature Integration Technology Inc. Rev 1.0 Sheet 1 of 6 Size Document Number Custom F71808E Date: Monday , August 16, 2010 87 Aug, 2010 V0.21P F71808E VCC5V RI1# CTS1# DSR1# RTS1# DTR1# SIN1 SOUT1 DCD1# 20 19 18 17 16 15 14 13 12 11 U2 VCC RY 1 RY 2 RY 3 DA1 DA2 RY 4 DA3 RY 5 GND +12V RA1 RA2 RA3 DY 1 DY 2 RA4 DY 3 RA9 -12V 1 2 3 4 5 6 7 8 9 10 +12V RIN1 CTSN1 DSRN1 RTSN1 DTRN1 SINN1 SOUTN1 DCDN1 -12V GND RIN1 DTRN1 CTSN1 SOUTN1 RTSN1 SINN1 DSRN1 DCDN1 5 9 4 8 3 7 2 6 1 P1 VSB3V VCC3V R12 4.7K RI1# DCD1# CTS1# DSR1# SIN1 R13 4.7K R14 4.7K R15 4.7K R16 4.7K UART DB9 UART 1 PORT INTERFACE If you do not use the UART port 1, please pull-up these pin to VCC3V. (for Device) J1 1 2 3 CON3 VCC5V 5VSB If you do not use the KBC, please pull-up these pin to 5VSB. F1 FUSE M-DIN_6-R JS1 1 2 3 6 5 4 R19 4.7K R20 4.7K L2 KDAT FB L4 KCLK C14 0.1U C15 100P C16 100P FB C17 0.1U Title F2 FUSE M-DIN_6-R JS2 1 2 3 6 5 4 R17 4.7K R18 4.7K L1 MDAT FB L3 MCLK C12 100P C13 100P FB PS2 MOUSE INTERFACE PS2 KEYBOARD INTERFACE Date: <F71808E> Feature Integration Technology Inc. Rev 1.0 Sheet 2 of 6 Size Document Number Custom UART_PS/2 Monday , August 16, 2010 88 Aug, 2010 V0.21P F71808E D1+ C18 DR22 VCORE R23 VLDT 1K_1% 1K_1% VCORE(VIN1) VLDT(VIN2) DR24 VDIMM R25 10K_1% 4.7K_1% D2+ C19 3300P 3300P THERMDC from CPU R21 4.7K THERMDA VCC3V Q3 PNP 3906 for SYSTEM OVT# VDIMM(VIN3) OVT Pull-up DIODE SENSING CIRCUIT VDIMM Input Level Must > 1V VREF R27 VDDA R28 10K_1% 10K_1% VIN4 D1+ VREF D2+ R30 VCC1.5V 10K_1% R29 10K 1% R26 10K 1% RT1 10K 1% THERMISTOR (for system) THERMISTOR (for system) VIN5 THERMISTOR SENSING CIRCUIT *VIN1 VIN2 VIN3 internal pull-down 320K ohm @ AMD mode. VOLTAGE SENSING. Temperature Sensing 5VSB (for Device) VSB3V R33 4.7K LED_VCC R31 4.7K PLED Q4 LED_VSB VSB3V R34 4.7K 5VSB (for Device) R32 4.7K SUSLED Q5 T RT2 T 10K 1% Title <F71808E> Feature Integration Technology Inc. Rev 1.0 Sheet 3 of 6 Size Document Number Custom HWM Date: Monday , August 16, 2010 89 Aug, 2010 V0.21P F71808E +12V VCC5V R35 10K FANCTL1 R37 100 D2 1N4148 C20 + 47U 4 HEADER 4 3 2 1 JP1 R38 27K R39 10K C21 0.1U FANIN1 R36 4.7K (4 PIN FAN Control) PWM FAN 1 SPEED CONTROL 12V +12V R41 4.7K 8 U3A 1 LM358 JP3 R50 10K C23 47u 3 2 1 CON3 C24 D3 1N4148 JP2 3 2 1 HEADER 3 3 R44 4.7K R46 27K R49 10K C25 0.1U R52 3.9K FANCTL2 2 + 4 R40 R42 4.7K 4.7K Q7 PNP PMOS Q6 D4 1N4148 R45 4.7K R47 27K 0.1u R51 10K FANIN2 VCC3V R43 4.7K R48 330 FANCTL2 C22 Q8 + MOSFET N 2N7002 47U FANIN2 PWM FAN 2 SPEED CONTROL +12V DC FAN Control with OP 2 12V R54 4.7K R53 R55 4.7K 4.7K Q9 PNP 8 D5 1N4148 JP4 3 2 1 HEADER 3 U3B 7 PMOS Q10 D6 1N4148 R58 4.7K JP5 C27 47u 3 2 1 CON3 R62 27K C29 0.1u R64 10K FANIN3 VCC3V R56 4.7K R60 330 R57 4.7K R59 27K R61 10K C28 0.1U 5 FANCTL3 FANIN3 6 + 4 FANCTL3 C26 Q11 + MOSFET N 2N7002 47U LM358 R63 10K R65 3.9K PWM FAN 3 SPEED CONTROL DC FAN Control with OP 3 FAN CONTROL FOR PWM OR DC Title <F71808E> Feature Integration Technology Inc. Rev 1.0 Sheet 4 of 6 Size Document Number Custom FAN Date: Monday , August 16, 2010 90 Aug, 2010 V0.21P F71808E VCC3V R69 4.7K VCC3V R70 4.7K VLDT_EN VCORE_EN PECI R68 100K (avoid pre-bios floating) PECI_Client Power Sequence Pull-up INTEL PECI Client Title <F71808E> Feature Integration Technology Inc. Rev 1.0 5 of 6 Size Document Number Custom AMDTSI/PECI & Power Sequence Date: Monday , August 16, 2010 Sheet 91 Aug, 2010 V0.21P F71808E VCC3V CPU 1 3 2 1K-8P4R 4 1K-8P4R NORTH BRIDGE IDE ATA 133 PCIRST1# PCIRST1# PCIRST2# VSB3V FRONT PANEL VSB5V (from ATX) 1 SATA*2 PCIRST2# .... .... SOUTH BRIDGE 2 R72 4.7K R74 1 33 2 7 RESET PSW- 8 R73 12 2 C30 0.1UF 5 RSTGND PSW+ 6 -PWR_BTN 1 2 R71 4.7K 1 Front Panel LRESET# RSTCON# F71808E PSON# PWSIN# PCI S3# PWSOUT# RSMRST# PCIRST3# VSB5V (from ATX) 1 R76 4.7K -12V 2 ATX1 3V3 3V3 -12V 3V3 GND GND PS-ON 5V GND GND GND 5V GND GND -5V PW-OK 5V 5VSB 5V 12V 5VSB (After Control ) 1 2 R77 4.7K 1 3 1 1K 2 4.7K 4 4.7K 2 VSB3V VCC3V PCLK_1,2,3(33MHz) VCC5V ATX CONNECTOR 1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 VCC3V VCC5V +12V VSB5V TC1 22uF ATX_PWR_GD ATX CONNECTOR 2 Title <F71808E> Feature Integration Technology Inc. Rev 1.0 Sheet 6 of 6 Size Document Number Custom Example_ACPI Date: Monday , August 16, 2010 Figure 20 F71808EU Application Circuit 92 Aug, 2010 V0.21P |
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